OX16C950-TQBG OXFORD SEMICONDUCTOR, OX16C950-TQBG Datasheet - Page 10

• Manufacturer Part Number: OX16C950-TQBG
• Description: IC, UART, 1CH, SMD, TQFP48, 950
• Manufacturer: OXFORD SEMICONDUCTOR

Specifications of OX16C950-TQBG

• No. Of Channels: 1
• Data Rate: 15Mbps
• Uart Features: Tx/Rx FIFO INT TRIG
• Supply Voltage Range: 3V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS-0031 Sep 05
OXFORD SEMICONDUCTOR LTD.
PLCC
Serial port pins
13
36
37
11
40
17
10
41
42
43
TQFP
8
32
33
7
38
39
40
41
12
5
Dir
O
O
O
O
O
O
I
I
I
I
I
I
I
I
O
I
1
Name
SOUT
IrDA_Out
RTS#
DTR#
485_EN
Tx_Clk_Out
SIN
IrDA_In
CTS#
DSR#
Rx_Clk_In
DCD#
RI#
Tx_Clk_In
BDOUT#
RCLK
Description
Transmitter serial data output.
This pin is re-defined to IrDA output when IrDA mode is enabled, i.e. MCR[6]
set in Enhanced mode.
Active-low Request-To-Send output. Whenever the automated RTS# flow
control is enabled, the RTS# pin is de-asserted and re-asserted if the receiver
FIFO reaches or falls below a pair of programmed flow control thresholds,
respectively. This pin’s state is controlled by bit 1 of the MCR. RTS may also
be used as a general-purpose output.
Active-low modem Data-Terminal-Ready output. Whenever the automated
DTR# flow control is enabled, the DTR# pin is asserted and de-asserted if the
receiver FIFO reaches or falls below a pair of programmed flow control
thresholds, respectively. The state is set by bit 0 of the MCR. DTR may also
be used as a general purpose output.
In RS485 half-duplex mode, the DTR# pin may be programmed to reflect the
state of the transmitter empty bit (or it’s inverse) to automatically control the
direction of the RS485 transceiver buffer (see ACR[4:3]).
Transmitter 1x (or baud rate generator output) clock. For isochronous
applications, the 1x (or Nx) transmitter clock may be asserted on the DTR#
pin (see CKS[5:4]).
Receiver serial data input.
This pin is re-defined to IrDA input when IrDA mode is enabled, i.e. MCR[6]
set in Enhanced mode.
Active-low Clear-To-Send input. Whenever the automated CTS# flow control
is enabled and the CTS# pin is de-asserted, the transmitter will complete the
current character and enter the idle mode until the CTS# pin is re-asserted.
However, flow control characters are transmitted regardless of the state of the
CTS# pin. The state of this pin is reflected in bit 4 of the MSR. It can also be
used as a general-purpose input.
Active-low modem Data-Set-Ready input. Whenever the automated DSR#
flow control is enabled and the DSR# pin is de-asserted, the transmitter will
complete the current character and enter the idle mode until the DSR# pin is
re-asserted. However, flow control characters are transmitted regardless of
the state of the DSR# pin. The state of this pin is reflected in bit 5 of the
MSR. It can also be used as a genera- purpose input.
External receiver clock for isochronous applications. The Rx_Clk_In is
selected when CKS[1:0] = ‘01’.
Active-low modem Data-Carrier-Detect input. The state of this pin is reflected
in bit 7 of the MSR. It can also be used as a general-purpose input
Active-low modem Ring-Indicator input. The state of this pin is reflected in bit
6 of the MSR. It can also be used as a general-purpose input. RI can be
configured as tx and rx for a 1x clock in isochronous operation.
External transmitter clock. This clock can be used by the transmitter (and by
the receiver indirectly) when CKS[6]=’1’.
Baud out. BDOUT# is a Nx (usually 16x, see TCR) clock signal for the
transmitter. It is the output of the baud generator module. The receiver can
use this clock by connecting BDOUT# to the RCLK pin or setting CKS[1:0] to
’10’ where BDOUT# will be connected to RCLK internally. In this case setting
CKS[2] to ‘1’ will disable the BDOUT# pin to conserve power.
Receiver clock. RCLK is the Nx (usually 16x, see TCR) baud rate clock for
the receiver.
External—Free Release
OX16C950 rev B
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