OX16C950-TQBG OXFORD SEMICONDUCTOR, OX16C950-TQBG Datasheet - Page 26

• Manufacturer Part Number: OX16C950-TQBG
• Description: IC, UART, 1CH, SMD, TQFP48, 950
• Manufacturer: OXFORD SEMICONDUCTOR

Specifications of OX16C950-TQBG

• No. Of Channels: 1
• Data Rate: 15Mbps
• Uart Features: Tx/Rx FIFO INT TRIG
• Supply Voltage Range: 3V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Level 4:
Modem change interrupt (ISR[5:0]=’000000’):
This interrupt is set by a modem change flag (MSR[0],
MSR[1], MSR[2] or MSR[3]) becoming active due to
changes in the input modem lines. This interrupt is cleared
following a read of the MSR.
Level 5:
Receiver in-band flow control (XOFF) detect interrupt,
Receiver special character (XOFF2) detect interrupt,
Receiver special character 1, 2, 3 or 4 interrupt or
9
A level 5 interrupt can only occur in Enhanced-mode when
any of the following conditions are met:
•
•
•
It is cleared on an ISR read of a level 5 interrupt.
Level 6:
CTS or RTS changed interrupt (ISR[5:0]=’100000’):
This interrupt is set whenever either of the CTS# or RTS#
pins changes state from low to high. It is cleared on an ISR
read of a level 6 interrupt.
10.4
For a channel to go into sleep mode, all of the following
conditions must be met:
•
•
•
•
•
•
•
•
A read of IER[4] (or IER[5] if a 1 was written to that bit
instead) shows whether the power-down request was
successful. The UART will fully retain its programmed state
whilst in power-down mode.
The channel will automatically exit power-down mode when
any of the conditions 1 to 7 becomes false. It may be
woken manually by clearing IER[4] (or IER[5] if
alternate sleep mode is enabled).
DS-0031 Sep 05
th
OXFORD SEMICONDUCTOR LTD.
Sleep mode operation is not available in IrDA mode.
Bit set interrupt in 9-bit mode (ISR[5:0]=’010000’):
A valid XOFF character is received while in-band flow
control is enabled.
A received character matches XOFF2 while special
character detection is enabled.
A received character matches special character 1, 2, 3
or 4 in 9-bit mode (see section 15.9).
Sleep mode enabled (IER[4]=1 in 650/950 modes, or
IER[5]=1 in 750 mode):
The transmitter is idle, i.e. the transmitter shift register
and FIFO are both empty.
SIN is high.
The receiver is idle.
The receiver FIFO is empty (LSR[0]=0).
The UART is not in loopback mode (MCR[4]=0).
Changes on modem input lines have been
acknowledged (i.e. MSR[3:0]=0000).
No interrupts are pending.
Sleep Mode
the
External—Free Release
11
11.1
MCR[0]: DTR
logic 0 ⇒ Force DTR# output to inactive (high).
logic 1 ⇒ Force DTR# output to active (low).
Note that DTR# can be used for automatic out-of-band flow
control when enabled using ACR[4:3] (see section 15.3).
MCR[1]: RTS
logic 0 ⇒ Force RTS# output to inactive (high).
logic 1 ⇒ Force RTS# output to active (low).
Note that RTS# can be used for automatic out-of-band flow
control when enabled using EFR[6] (see section 13.4).
MCR[2]: OUT1
logic 0 ⇒ Force OUT1# output low when loopback mode
logic 1 ⇒ Force OUT1# output high.
MCR[3]: OUT2/External interrupt enable
logic 0 ⇒ Force OUT2# output low when loopback mode
logic 1 ⇒ Force OUT2# output high. If INTSEL# is low
MCR[4]: Loopback mode
logic 0 ⇒ Normal operating mode.
logic 1 ⇒ Enable local loop-back mode (diagnostics).
In local loop-back mode, the transmitter output (SOUT) and
the four modem outputs (DTR#, RTS#, OUT1# and
OUT2#) are set in-active (high), and the receiver inputs
SIN, CTS#, DSR#, DCD#, and RI# are all disabled.
Internally the transmitter output is connected to the receiver
input and DTR#, RTS#, OUT1# and OUT2# are connected
to modem status inputs DSR#, CTS#, RI# and DCD#
respectively.
M
Modem Control Register ‘MCR’
ODEM
is disabled.
is disabled. If INTSEL# is low the external
interrupt is in high-impedance state when
MCR[3] is cleared. If INTSEL# is high MCR[3]
does not affect the interrupt.
the external interrupt is enabled and operating
in normal active (forcing) mode when MCR[3]
is high. If INTSEL# is high MCR[3] does not
affect the interrupt.
I
NTERFACE
OX16C950 rev B
Page 26