OX16C950-TQBG OXFORD SEMICONDUCTOR, OX16C950-TQBG Datasheet - Page 9
![IC, UART, 1CH, SMD, TQFP48, 950](/photos/19/3/190350/42334692_sml.jpg)
OX16C950-TQBG
Manufacturer Part Number
OX16C950-TQBG
Description
IC, UART, 1CH, SMD, TQFP48, 950
Manufacturer
OXFORD SEMICONDUCTOR
Datasheet
1.OX16C950-TQBG.pdf
(50 pages)
Specifications of OX16C950-TQBG
No. Of Channels
1
Data Rate
15Mbps
Uart Features
Tx/Rx FIFO INT TRIG
Supply Voltage Range
3V To 5.25V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
TQFP
No. Of Pins
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
OX16C950-TQBG
Manufacturer:
SAMSUNG
Quantity:
450
4
DS-0031 Sep 05
OXFORD SEMICONDUCTOR LTD.
PLCC
Clock
18
19
23
Processor Interface
39
14, 15
16
29 -31
28
9 - 2
26
20
21
24
25
P
IN
D
ESCRIPTIONS
TQFP
14
15
21
35
9,
10
11
26 – 28
24
4 – 2,
47 – 43
22
16
17
19
20
Dir
I
O
IU
I
I
I
I
I
I/O
O
I
I
I
I
1
Name
XTLI
XTLO
CLKSEL
RESET
CS0,CS1
CS2#
A[2:0]
ADS#
DB[7:0]
DDIS
IOW#
IOW
IOR#
IOR
Description
Crystal oscillator input or external clock pin.
Maximum frequency 60 MHz @ 5V, 50 MHz @ 3.3V
Crystal oscillator output. Not used when an alternative TTL level clock is
applied to XTLI and can be left unconnected.
The state of this pin on power up configures the internal clock prescaler. This
pin has an internal pull-up. When CLKSEL pin is high the pre-scalar is
bypassed. Connect this pin to GND to enable the internal clock prescaler
(see section 14.2). The complement of this pin is loaded in MCR[7] after a
hardware reset.
This pin can also be used as an alternative external clock pin under software
control (replacing XTLI and thus reducing noise/power due to XTLO) for
embedded applications
Active-high hardware reset. Hardware reset is described in section 7.1. This
pin must be tied inactive when not in use.
Active-high chip select. All chip select pins must be active for the device to
be selected.
Active-low chip select.
Address lines to select channel registers.
Active-low address strobe. When ADS# signal is low, the address (A[2:0])
and chip select signal (CS0, CS1, CS2#) drive the internal logic, otherwise
they are latched at the level they were when low-to-high transition of ADS#
signal occurred. This pin is used when address and chip selects are not
stable during read or write cycles. If this functionality is not required, this pin
can be permanently tied to GND.
Eight-bit 3-state data bus.
Drive Disable. This pin goes active (high) when CPU is not reading from
OX16C950. This signal can be used to disable an external transceiver.
Active-low write strobe. When IOW# is used to write the chip, IOW should be
tied low (inactive).
Active-high write strobe. When IOW is used to write the chip, IOW# should be
tied high (inactive).
Active-low read strobe. When IOR# is used to read from the chip, IOR should
be tied low (inactive).
Active-high read strobe. When IOR is used to read from the chip, IOR#
should be tied high (inactive).
External—Free Release
OX16C950 rev B
Page 9