OX16C950-TQBG OXFORD SEMICONDUCTOR, OX16C950-TQBG Datasheet - Page 16

• Manufacturer Part Number: OX16C950-TQBG
• Description: IC, UART, 1CH, SMD, TQFP48, 950
• Manufacturer: OXFORD SEMICONDUCTOR

Specifications of OX16C950-TQBG

• No. Of Channels: 1
• Data Rate: 15Mbps
• Uart Features: Tx/Rx FIFO INT TRIG
• Supply Voltage Range: 3V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6
The three address lines select the various registers in the UART. Since there are more than 8 registers, selection of the registers
is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:
1. LCR[7]=1 enables the divider latch registers DLL and DLM.
2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables
3. ACR[7]=1 enables access to the 950 specific registers.
4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 18.
DS-0031 Sep 05
OXFORD SEMICONDUCTOR LTD.
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.
Register
650 mode
750 mode
950 mode
9-bit data
9-bit data
650/950
550/750
550/750
650/950
Name
MCR
Normal
Normal
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.
LSR
RHR
MSR
THR
IER
FCR
LCR
SPR
Mode
Mode
Mode
Mode
mode
mode
ISR
DLM
DLL
R
EGISTER
1,2
3,5
3
3,4
1
3
4
3
1
3
Address
000
000
001
010
010
011
100
101
110
111
000
001
D
ESCRIPTION
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
R
interrupt
prescale
Divisor
access
T
Bit 7
mask
Baud
Error
latch
Data
DCD
CTS
ABLES
RHR Trigger
RHR Trigger
Table 4: Standard 550 Compatible Registers
Unused
enabled
Unused
FIFOs
Level
Level
Tx Empty
interrupt
Bit 6
break
mode
mask
RTS
IrDA
Tx
RI
Unused
External—Free Release
XON-Any
Alternate
Special
Control
Divisor latch bits [15:8] (Most significant byte)
Detect
CTS &
Empty
Divisor latch bits [7:0] (Least significant byte)
Bit 5
mode
Force
Char.
sleep
parity
FIFO
(Enhanced mode)
RTS
Flow
THR
DSR
Size
Interrupt priority
Indexed control register offset value bits
THR Trigger
Temporary data storage register and
Level
Data to be transmitted
Unused
Internal
Unused
Enable
Bit 4
Sleep
Break
mode
Odd /
parity
Loop
Back
even
CTS
Rx
Data received
interrupt
Framing
Modem
(Int En)
Trigger
Enable
Mode /
enable
Bit 3
OUT2
Parity
mask
Delta
DMA
Error
DCD
Tx
Interrupt priority
(All modes)
interrupt
Number
RI edge
Rx Stat
data bit
Trailing
of stop
OUT1
Bit 2
Parity
9
mask
Flush
Error
THR
bits
th
Rx
OX16C950 rev B
interrupt
Overrun
THRE
Bit 1
mask
Flush
Delta
RHR
Error
DSR
RTS
Data length
interrupt
Interrupt
pending
RxRDY
RxRDY
Enable
data bit
Bit 0
mask
Delta
FIFO
9
DTR
CTS
Page 16
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Tx