AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 296

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

23.14.1
23.15 Interrupt system
296
AT90USB64/128
CRC Error (isochronous only)
Each time the current bank is full, the RXIN and the FIFOCON bits are set. This triggers an inter-
rupt if the RXINE bit is set. The firmware can acknowledge the USB interrupt by clearing the
RXIN bit. The Firmware read the data and clear the FIFOCON bit in order to free the current
bank. If the IN Pipe is composed of multiple banks, clearing the FIFOCON bit will switch to the
next bank. The RXIN and FIFOCON bits are then updated by hardware in accordance with the
status of the new bank.
A CRC error can occur during IN stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI/CRCERRI interrupt is triggered. This does not prevent the RXINI
interrupt from being triggered.
Example with 1 IN data bank
Example with 2 IN data banks
RXIN
FIFOCON
RXIN
FIFOCON
IN
IN
(to bank 0)
(to bank 0)
DATA
DATA
HW
HW
ACK
ACK
SW
SW
read data from CPU
read data from CPU
IN
BANK 0
BANK 0
(to bank 1)
DATA
SW
SW
IN
HW
ACK
(to bank 0)
read data from CPU
SW
DATA
BANK 1
HW
ACK
SW
read data from CPU
BANK 0
7593K–AVR–11/09