AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 30

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AT90USB647-MU

Manufacturer Part Number
AT90USB647-MU
Description
MCU, 8BIT, 64K FLASH, USB, 64QFN
Manufacturer
Atmel
Datasheets

Specifications of AT90USB647-MU

Controller Family/series
AT90
No. Of I/o's
48
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
16MHz
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
64KB
Oscillator Type
External, Internal
Package
64QFN EP
Device Core
AVR
Family Name
AT90
Maximum Speed
20 MHz
Ram Size
4 KB
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
48
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
Lead Free Status / Rohs Status
 Details

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5.5
5.5.1
5.5.2
30
External Memory Interface
AT90USB64/128
Overview
Using the External Memory Interface
With all the features the External Memory Interface provides, it is well suited to operate as an
interface to memory devices such as External SRAM and Flash, and peripherals such as LCD-
display, A/D, and D/A. The main features are:
When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM
becomes available using the dedicated External Memory pins (see
10-3 on page
Figure 5-4.
The interface consists of:
The control bits for the External Memory Interface are located in two registers, the External
Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.
• AD7:0: Multiplexed low-order address bus and data bus.
• A15:8: High-order address bus (configurable number of bits).
• ALE: Address latch enable.
• RD: Read strobe.
• WR: Write strobe.
Four different wait-state settings (including no wait-state).
Independent wait-state setting for different external Memory sectors (configurable sector size).
The number of bits dedicated to address high byte is selectable.
Bus keepers on data lines to minimize current consumption (optional).
79, and
External Memory with Sector Select
Table 10-9 on page
E xternal M emory
(0-60K x 8)
M emory C onfiguration A
83). The memory configuration is shown in
I nternal memory
L ower sector
U pper sector
SRW01
SRW00
SRW11
SRW10
0 x 0000
ISRAM end
XMem start
0 x FFFF
SRL[2..0]
Figure 2-1 on page
7593K–AVR–11/09
Figure
5,
Table
5-4.

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