AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 298

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

23.16.1
298
AT90USB64/128
General USB Host registers
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2 - RESUME - Send USB Resume
Set this bit to generate a USB Resume on the USB bus.
Cleared by hardware when the USB Resume has been sent. Clearing by software has no effect.
This bit should be set only when the start of frame generation is enable (SOFEN bit set).
• 1 - RESET - Send USB Reset
Set this bit to generate a USB Reset on the USB bus.
Cleared by hardware when the USB Reset has been sent. Clearing by software has no effect.
Refer to the USB reset section for more details.
• 0 - SOFEN - Start Of Frame Generation Enable
Set this bit to generate SOF on the USB bus in full speed mode and keep-alive in low speed
mode.
Clear this bit to disable the SOF generation and to leave the USB bus in Idle state.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6 - HWUPI
Host Wake-Up Interrupt
Set by hardware when a non-idle state is detected on the USB bus.This interrupt should be
enable only to wake up the CPU core from power down mode.
Shall be clear by software to acknowledge the interrupt. Setting by software has no effect.
• 5 - HSOFI - Host Start Of Frame Interrupt
Set by hardware when a SOF is issued by the Host controller. This triggers a USB interrupt
when HSOFE is set. When using the host controller in low speed mode, this bit is also set when
a keep-alive is sent.
Shall be cleared by software to acknowledge the interrupt. Setting by software has no effect.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
7
0
-
R
7
0
-
HWUPI
R
R/W
6
0
-
6
0
HSOFI
R
5
0
R/W
-
5
0
RXRSMI
R
4
0
R/W
-
4
0
RSMEDI
R
3
0
R/W
-
3
0
RESUME
R/W
RSTI
2
0
R/W
2
0
RESET
DDISCI
R/W
1
0
R/W
1
0
SOFEN
DCONNI
R/W
R/W
0
0
7593K–AVR–11/09
0
0
UHCON
UHINT