AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 8
AT90USB647-MU
Manufacturer Part Number
AT90USB647-MU
Description
MCU, 8BIT, 64K FLASH, USB, 64QFN
Manufacturer
Atmel
Specifications of AT90USB647-MU
Controller Family/series
AT90
No. Of I/o's
48
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
16MHz
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
64KB
Oscillator Type
External, Internal
Package
64QFN EP
Device Core
AVR
Family Name
AT90
Maximum Speed
20 MHz
Ram Size
4 KB
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
48
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
Lead Free Status / Rohs Status
Details
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2.2.8
2.2.9
2.2.10
2.2.11
2.2.12
2.2.13
2.2.14
2.2.15
2.2.16
2.2.17
8
AT90USB64/128
Port E (PE7..PE0)
Port F (PF7..PF0)
D-
D+
UGND
UVCC
UCAP
VBUS
RESET
XTAL1
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the AT90USB64/128 as listed on
page
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D-
connector pin with a serial 22 Ohms resistor.
USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22 Ohms resistor.
USB Pads Ground.
USB Pads Internal Regulator Input supply voltage.
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-
itor (1µF).
USB VBUS monitor and OTG negociations.
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in
58. Shorter pulses are not guaranteed to generate a reset.
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
87.
Table 8-1 on page
7593K–AVR–11/09
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