AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 322
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AT90USB647-MU
Manufacturer Part Number
AT90USB647-MU
Description
MCU, 8BIT, 64K FLASH, USB, 64QFN
Manufacturer
Atmel
Specifications of AT90USB647-MU
Controller Family/series
AT90
No. Of I/o's
48
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
16MHz
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
64KB
Oscillator Type
External, Internal
Package
64QFN EP
Device Core
AVR
Family Name
AT90
Maximum Speed
20 MHz
Ram Size
4 KB
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
48
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
Lead Free Status / Rohs Status
Details
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Price
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25.6.2
25.6.3
25.6.4
322
AT90USB64/128
Analog Noise Canceling Techniques
Offset Compensation Schemes
ADC Accuracy Definitions
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
Figure 25-9. ADC Power Connections
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-
surements as much as possible. The remaining offset in the analog path can be measured
directly by selecting the same channel for both differential inputs. This offset residue can be then
subtracted in software from the measurement results. Using this kind of software based offset
correction, offset on any channel can be reduced below one LSB.
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior:
a. Keep analog signal paths as short as possible. Make sure analog tracks run over
b. The AV
c. Use the ADC noise canceler function to reduce induced noise from the CPU.
d. If any ADC port pins are used as digital outputs, it is essential that these do not
the analog ground plane, and keep them well away from high-speed switching digi-
tal tracks.
via an LC network as shown in
switch while a conversion is in progress.
CC
pin on the device should be connected to the digital V
Analog Ground Plane
100nF
Figure
(ADC7) PF7
(ADC6) PF6
(ADC5) PF5
(ADC4) PF4
(ADC3) PF3
(ADC2) PF2
(ADC1) PF1
(ADC0) PF0
(AD0) PA0
25-9.
AREF
AVCC
GND
GND
VCC
51
52
53
54
55
56
57
58
59
60
61
61
62
62
63
63
64
64
1
n
-1.
CC
supply voltage
REF
7593K–AVR–11/09
in 2
n
steps
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