AC80566UC005DE S LB2C Intel, AC80566UC005DE S LB2C Datasheet
AC80566UC005DE S LB2C
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... Intel Atom™ Processor Z5xx Series Datasheet ® — For the Intel Atom™ Processor Z560 ∆ ∆ Z520 , Z515 , Z510 June 2010 ∆ , Z550 ∆ ∆ , and Z500 Process Technology ∆ ∆ ∆ ∆ , Z540 , Z530 , Document Number: 319535-003US ...
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... Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 visiting ∆ ...
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... Enhanced Intel SpeedStep® Technology ................................................... 23 2.4 Enhanced Low-Power States .................................................................... 24 2.5 FSB Low Power Enhancements................................................................. 25 2.5.1 2.6 Intel® Burst Performance Technology (Intel® BPT) .................................. 26 3 Electrical Specifications ..................................................................................... 27 3.1 FSB, GTLREF, and CMREF ........................................................................ 27 3.2 Power and Ground Pins ........................................................................... 27 3.3 Decoupling Guidelines ............................................................................ 28 3 ...
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... Table 7. Voltage and Current Specifications for the Intel® Atom™ Processor Z560, Z550, Z540, Z530, Z520, and Z510 ....................................................... 35 Table 8. Voltage and Current Specifications for the Intel® Atom™ Processor Z500 ... 37 Table 9. Voltage and Current Specifications for the Intel® Atom™ Processor Z515 ... 38 Table 10 ...
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... Number Number 319535 001 • Initial release 319535 002 • Updated information about Intel • Added Intel • Changed VccBoot value to VccLFM in Table 7 and • Added new Table 9, Voltage and Current • Removed EMTTM references not a supported 319535 003 • Added Z560 information • ...
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... Note: In this document, Intel Atom processor Z5xx series refers to the Intel Atom processors Z560, Z550, Z540, Z530, Z520, Z515, Z510, and Z500. Note: In this document, the Intel Atom processor Z5xx series is referred to as “processor”. The Intel® System Controller Hub (Intel® SCH) is referred to as the “Intel® SCH”. ...
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... Execute Disable Bit support for enhanced security • Intel® Burst Performance Technology (Intel® BPT) (Intel Atom processor Z515 only) 8 Introduction Datasheet ...
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... D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). Refers to the interface between the processor and system core logic (also known as the Intel® SCH chipset components). Advanced Gunning Transceiver Logic is used to refer to Assisted GTL+ signaling technology on some Intel processors. ...
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... Deeper Sleep (C4) CC Fuse Power Supply I for Intel Atom processors Z5xx Series Recommended Design CCDES Target power delivery (Estimated) I for Intel Atom processors Z5xx Series is the number that can be use reflection on a battery life estimates I Auto-Halt CC I Stop-Grant CC I Deep Sleep ...
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... Material and concepts available in the following documents may be beneficial when reading this document. Table 1. References Intel® System Controller Hub (Intel® SCH) Datasheet Intel® Atom™ Processor Z5xx Series Specification Update Intel® 64 and IA-32 Architectures Software Developer's Manuals ...
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This page intentionally left blank. Introduction Datasheet ...
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Low Power Features 2 Low Power Features 2.1 Clock Control and Low-Power States The processor supports low power states at the thread level and the core/package level. Thread states (TCx) loosely correspond to ACPI processor power states (Cx). A thread ...
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Figure 1. Thread Low-Power States C1/ MWAIT † C4 halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted) † — STPCLK# ...
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... FSB interrupt messages. RESET# will cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more information. ...
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... TC1 or greater thread state. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor to return to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference and Volume 2B: Instruction Set Reference, N-Z, for more information ...
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... The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state and is only a transition state for Intel Atom processor Z5xx series. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertion while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation ...
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... Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state and is also only a transition state for the Intel Atom processor Z5xx series. BCLK may be stopped during the Deep Sleep state for additional platform level power savings ...
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... T5000/T7000 C5 implementation. In the Intel Atom processor Z5xx series C5, the V will not be powered below the retention of caches voltage— there is no need to initialize the processor’s caches exit, and C5 is not architecturally enumerated to software. This state is the same as the Intel Atom processor Z5xx series C5 state. 2.1.1.4 C6 State new low power state being introduced on the Intel Atom processor Z5xx series ...
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... Intel® Deep Power Down Technology State (Package C6 State) When both threads have entered the C6 state and the L2 cache has been shrunk down to zero ways, the processor will enter the Package Deep Power Down Technology state so, the processor saves its architectural states in the on-die SRAM that ...
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... Figure 5. Exit Latency Table C0 (HFM) TDP C0 (LFM Datasheet C1 Similar to C1 but Intel® Both threads halted SCH blocks interrupts Most clocks off C1E C1 plus frequency and VID at LFM C2 plus PLLs off; VID = cache retention Vcc Some L2 cache off ...
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... L2 cache shrink prevention may be enabled as needed on occasion through an MWAIT(C4) sub-state field. If shrink prevention is enabled, the processor does not enter Intel Deeper Sleep state or C6 since the L2 cache remains valid and in full size. 22 Low Power Features ...
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... Enhanced thermal management features: Digital Thermal Sensor and Out of Specification detection Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in case of unsuccessful TM2 transition. Datasheet is changed through the VID pin mechanism. ...
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... Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low-power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in the Stop-Grant and Deeper Sleep states ...
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Low Power Features 2.5 FSB Low Power Enhancements The processor incorporates FSB low power enhancements: • BPRI# control for address and control input buffers • Dynamic Bus Parking • Dynamic On Die Termination disabling • Low V (I/O termination voltage) ...
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... BPT) The processor supports ACPI Performance States (P-States). The P-state referred will be a request for Intel® Burst Performance Technology (Intel® BPT). Intel BPT opportunistically, and automatically, allows the processor to run faster than the marked frequency if the part is operating within the thermal design limits of the platform ...
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Electrical Specifications 3 Electrical Specifications This chapter contains signal group descriptions, absolute maximum ratings, voltage identification, and power sequencing. The chapter also includes DC specifications. 3.1 FSB, GTLREF, and CMREF The processor supports two kinds of signalling protocol: Complementary Metal ...
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Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag ...
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Electrical Specifications Table 3. Voltage Identification Definition VID6 VID5 ...
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VID6 VID5 ...
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Electrical Specifications 3.6 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, ...
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Implementation of a source synchronous data bus determines the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, and so on.) and ...
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Electrical Specifications 3.10 CMOS Asynchronous Signals CMOS input signals are shown in Table 5. Legacy output FERR#, IERR#, and other non- AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These signals do not have setup or hold time ...
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Table 6. Processor Absolute Maximum Ratings Symbol T STORAGE V CC, VCCP, VCCPC6 VCCA VinAGTL+ VinAsynch_CMOS NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Storage temperature is applicable to storage ...
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... Electrical Specifications Table 7. Voltage and Current Specifications for the Intel® Atom™ Processor Z560, Z550, Z540, Z530, Z520, and Z510 Symbol Parameter FSB BCLK Frequency Frequency V HFM V @ Highest Frequency Mode (HFM LFM V @ Lowest Frequency Mode (LFM Default V Voltage for Initial Power Up ...
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... VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or Enhanced Halt State). Typical AVID range ...
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... VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or Enhanced Halt State). Typical AVID range ...
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... V while exiting C6 (Deep Power Down Technology State) at least 5 µs before V ramps to LFM VID. In addition, V CC_CORE during V CCP Table 9. Voltage and Current Specifications for the Intel® Atom™ Processor Z515 Symbol Parameter FSB BCLK Frequency Frequency V @ Burst Frequency Mode (BFM) ...
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... V and V CCP 13. The V power supply needs to be set to 0.3 to 0.4 V during C6 power state. CC 14. The Intel Atom processor Z515 enables Intel® Burst Performance Technology (Intel® BPT). Datasheet Min. — — — ...
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Figure 6. Active V and Max[HFM][LFM Max[HFM][LFM] CC Nom[HFM][LFM Min[HFM][LFM] CC Min[HFM][LFM Loadline V (V) CC Slope = -5.7 mV/A at package VCC_SENSE, VSS_SENSE pins. Differential ...
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Electrical Specifications Figure 7. Deeper Sleep Max CC_CORE (Deeper Sleep) V Max CC_CORE, DC (Deeper Sleep) V Nom CC_CORE (Deeper Sleep) V CC_CORE, DC (Deeper Sleep) V CC_CORE (Deeper Sleep) Datasheet and I Loadline CC V (V) ...
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Table 10. FSB Differential BCLK Specifications Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Crossing Voltage CROSS Range of Crossing Points ∆V CROSS V Differential Output Swing SWING I Input Leakage Current LI Cpad Pad ...
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Electrical Specifications Table 11. AGTL+/CMOS Signal Group DC Specifications Symbol Parameter V I/O Voltage CCP V I/O Voltage for C6 CCPC6 GTLREF GTL Reference Voltage CMREF CMOS Reference Voltage R Compensation Resistor COMP R Termination Resistor ODT V Input High ...
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Table 12. Legacy CMOS Signal Group DC Specifications Symbol Parameter V I/O Voltage CCP V C6 I/O Voltage for C6 CCP V Input High Voltage IH V Input Low Voltage CMOS IL V Output High Voltage OH V Output Low ...
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Electrical Specifications 3.13 AGTL+ FSB Specifications Termination resistors are not required for most AGTL+ signals, as these are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal’s voltage with ...
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... This chapter describes the package specifications, pinout assignments, and signal descriptions. 4.1 Package Mechanical Specifications The processor will be available in 512 KB, 441 pins in FCBGA8 package. The package dimensions are shown in Figure 8. 4.1.1 Processor Package Weight The Intel Atom processor Z5xx series package weight is 0.475 g. Datasheet 47 ...
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Figure 8. Package Mechanical Drawing 48 Package Mechanical Specifications and Pin Information Datasheet ...
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Package Mechanical Specifications and Pin Information 4.2 Processor Pinout Assignment Figure 9 and Figure 10 are graphic representations of the processor pinout assignments. Table 14 lists the pinout by signal name. Figure 9. Pinout Diagram (Top View, Left Side) AJ ...
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Figure 10. Pinout Diagram (Top View, Right Side TMS TDO 2 VID[5] TDI TCK 3 VSS VSS 4 VID[1] VID[2] VID[4] 5 VID[0] RESET# 6 VCC VCC VSS 7 VSS VSS 8 VCC VCC VCC ...
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Package Mechanical Specifications and Pin Information Table 14. Pinout Arranged by Signal Name Signal Name A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# ...
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Signal Name D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DBSY# DEFER# DINV[0]# 52 Package Mechanical Specifications and Pin Information ...
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Package Mechanical Specifications and Pin Information Signal Name TEST4 THERMTRIP# THRMDA THRMDC TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Datasheet ...
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Signal Name VCCPC6 VCCPC6 VCCPC6 VCC_SENSE VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VSS VSS/NCTF VSS/NCTF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 54 Package Mechanical Specifications and Pin Information ...
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Package Mechanical Specifications and Pin Information Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Datasheet Ball # Signal Name K9 ...
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Signal Description Table 15. Signal Description Signal Name A[31:3]# A20M# ADS# ADSTB[1:0]# BCLK[1:0] BNR# 56 Type A[31:3]# (Address) defines a 2 space. In subphase 1 (one) of the address phase, these pins transmit the address of a transaction. In ...
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... BR0# is used by the processor to request the bus. The I/O arbitration is done between the processor (Symmetric Agent) and Intel® SCH (High Priority Agent). BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 4 defines the possible combinations of the signals and the frequency associated with each combination. The ...
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... Sleep State to the Deep Sleep state. In order I to return to the Sleep State, DPSLP# must be de-asserted. DPSLP# is driven by the SCH chipset. DPWR control signal from the Intel® SCH used to reduce I power on the processor data bus input buffers. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus ...
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... STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MSDOS*- type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service ...
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Signal Name INIT# LINT[1:0] LOCK# PRDY# PREQ# PROCHOT# 60 Type INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during ...
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Package Mechanical Specifications and Pin Information Signal Name PWRGOOD REQ[4:0]# RESET# RS[2:0]# RSVD Reserved SLP# SMI# Datasheet Type PWRGOOD (Power Good processor input. The processor requires this signal clean indication that the clocks and power ...
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Signal Name STPCLK# TCK TDI TDO TEST[1:4] THRMTRIP# THRMDA THRMDC TMS TRDY# TRST# VCCA VCC VSS VSS/NCTF 62 Type STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop- Grant ...
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Package Mechanical Specifications and Pin Information Signal Name VID[6:0] VCCP VCCPC6 VCC_SENSE VSS_SENSE Datasheet Type VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (V generations of processors, these are CMOS signals that are driven ...
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... Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.2. In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification ...
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... Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T Refer to Section 5.1 for more details. 4. ...
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... Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T Refer to Section 5.1 for more details. 4. ...
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... Thermal Specifications The processor incorporates three methods of monitoring die temperature—Digital Thermal Sensor, Intel Thermal Monitor, and the Thermal Diode. The Intel Thermal Monitor (detailed in Section 5.1.2) must be used to determine when the maximum specified processor junction temperature has been reached. ...
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... Transistor Ideality Beta R Series Resistance T NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized across a temperature range of 50–100 °C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, nQ, represents the deviation from ideal transistor model behavior ...
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... After automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications. Intel recommends TM1 and TM2 be enabled on the processor ...
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... Enhanced Intel SpeedStep Technology target frequency point. The TCC may also be activated using on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written the TCC will be activated immediately independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable using bits 3:1 of the same ACPI Intel Thermal Monitor control register ...
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... Changes to the temperature can be detected using two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts using the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details. ...
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... TCC temperature trip point will have its core clocks modulated. If TM2 is enabled and the core is above TCC temperature trip point, it will enter the lowest programmed TM2 performance state important to note that Intel recommends both TM1 and TM2 to be enabled. When PROCHOT# is driven by an external agent, if only TM1 is enabled on the core, then the processor core will have the clocks modulated ...