AC80566UC005DE S LB2C Intel, AC80566UC005DE S LB2C Datasheet - Page 20

• Manufacturer Part Number: AC80566UC005DE S LB2C
• Description: MPU, ATOM PROCESSOR, Z510, U-FCBGA
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of AC80566UC005DE S LB2C

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 400MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 441
• Supply Voltage Range: 0.75V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.1.1.4.1
20
TC0
Package
TC1
Figure 3. Deep Power Down Technology Entry Sequence
Figure 4. Deep Power Down Technology Exit Sequence
Thread 0
Thread 1
C6
MWAIT C6
or Level 6
I/O Read
Intel® Deep Power Down Technology State (Package C6 State)
When both threads have entered the C6 state and the L2 cache has been shrunk down
to zero ways, the processor will enter the Package Deep Power Down Technology
state. To do so, the processor saves its architectural states in the on-die SRAM that
resides in the V
core voltage (closer to 0.3 V). The processor is now in an extremely low-power state.
While in this state, the processor does not need to be snooped as all the caches were
flushed before entering the C6 state.
The Deep Power Down Technology exit sequence is triggered by the chipset when it
detects a break event. It de-asserts the DPRSTP#, DPSLP#, SLP#, and STPCLK# pins
to return to C0. At DPSLP# de-assertion, the core V
the processor starts up its internal PLLs. At SLP# de-assertion the processor is reset
and the architectural state is read back into the threads from an on-die SRAM.
Refer to Figure 3 and Figure 4 for Deep Power Down Technology entry sequence and
exit sequences.
NOTE: Deep Power Down Technology is referred to as C6 in the above figure.
MWAIT C6
or Level 6
I/O Read
DPRST#
deassert
State
Save
Shrink
L2
TC6
deassert
CCP
DPSL#
domain. At this point, the core V
State
Save
TC6
Reset
H/W
I/O Read
Level 6
deassert
SLP#
Ucode reset
STPCLK#
Ucode reset
and state
assert
restore
and state
(TC1)
restore
(TC0)
CC
CC
assert
SLP#
will be dropped to the lowest
ramps up to the LFM value and
DPSLP#
assert
STPCLK#
Low Power Features
deassert
DPRSTP#
assert
TC0
Datasheet
Package
TC0
C6