AC80566UC005DE S LB2C Intel, AC80566UC005DE S LB2C Datasheet - Page 19

• Manufacturer Part Number: AC80566UC005DE S LB2C
• Description: MPU, ATOM PROCESSOR, Z510, U-FCBGA
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of AC80566UC005DE S LB2C

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 400MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 441
• Supply Voltage Range: 0.75V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low Power Features
2.1.1.3.4
2.1.1.4
Datasheet
Intel® Atom™ Processor Z5xx Series C5
As mentioned previously in this document, each C-state has latency and transitory
power costs associated with entering/exiting idle states. When the processor is
interrupted, it must awake to service requests. If these requests occur at a high
frequency, it is possible that more power will be consumed entering/exiting the states
than will be saved. To alleviate this concern, the Intel Atom processor Z5xx series
implements a new state called “Intel Atom processor Z5xx series C5”. The Intel Atom
processor Z5xx series C5 is not exposed to software. The only way to enter the C5
state is using a hardware promotion of C4 (with the cache ways shrunk to zero).
When the processor is in C4, the chipset assumes the processor has data in its cache.
Often, the processor has fully flushed its cache. To avoid waking up the processor to
service snoops when there is no data in its caches, the processor will automatically
promote C4 requests to C5 (when the cache is flushed). The chipset treats C5 as a
non-snoopable state. Therefore, all snoops will be completed from the I/O DMA
masters without waking up the processor.
While similar, the Intel Atom processor Z5xx series C5 differs from the Core 2 Duo
T5000/T7000 C5 implementation. In the Intel Atom processor Z5xx series C5, the V
will not be powered below the retention of caches voltage— there is no need to
initialize the processor’s caches on a C5 exit, and C5 is not architecturally enumerated
to software. This state is the same as the Intel Atom processor Z5xx series C5 state.
C6 State
C6 is a new low power state being introduced on the Intel Atom processor Z5xx
series. C6 behavior is the same as Intel Enhanced Deeper Sleep with the addition of
an on-die SRAM. This memory saves the processor state allowing the processor to
lower its main core voltage closer to 0 V. It is important to note that V
lower while only 1 (one) thread is in C6 state.
The processor threads can enter the C6 state by initiating a P_LVL6 I/O read to the
P_BLK or an MWAIT(C6) instruction. To enter C6, the processor’s caches must be
flushed. The primary method to enter C6 used by newer operating systems (that
support MWAIT) will be through the MWAIT instruction.
When the thread enters C6, it saves the processor state that is relevant to the
processor context in an on-die SRAM that resides on a separate power plane V
power supply). This allows the core V
including 0 V. The microcode performs the save and restore of the processor state on
entry and exit from C6 respectively.
CC
to be lowered to any arbitrary voltage
CC
cannot be
CCP
(I/O
CC
19