AC80566UC005DE S LB2C Intel, AC80566UC005DE S LB2C Datasheet - Page 31

• Manufacturer Part Number: AC80566UC005DE S LB2C
• Description: MPU, ATOM PROCESSOR, Z510, U-FCBGA
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of AC80566UC005DE S LB2C

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 400MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 441
• Supply Voltage Range: 0.75V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications
3.6
3.7
3.8
3.9
Datasheet
Table 4. BSEL[2:0] Encoding for BCLK Frequency
Catastrophic Thermal Protection
The processor supports the THERMTRIP# signal for catastrophic thermal protection.
An external thermal sensor should also be used to protect the processor and the
system against excessive temperatures. Even with the activation of THERMTRIP#,
which halts all processor internal clocks and activity, leakage current can be high
enough such that the processor cannot be protected in all conditions without the
removal of power to the processor. If the external thermal sensor detects a
catastrophic processor temperature of 120°C (maximum), or if the THERMTRIP#
signal is asserted, the V
prevent permanent silicon damage due to thermal runaway of the processor.
THERMTRIP# functionality is not ensured if the PWRGOOD signal is not asserted.
Reserved and Unused Pins
RSVD[3:0] must be tied directly to V
operation of the processor. All other RSVD signals can be left as No Connect.
Connection of these pins to V
result in component malfunction or incompatibility with future processors. See
Section 4.2 for a pin listing of the processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (V
unconnected.
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate
chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 4.
NOTE: All other bus selections reserved.
FSB Signal Groups
To simplify the following discussion, the FSB signals have been combined into groups
by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF
as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+
input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+
Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when
driving.
BSEL[2]
H
L
BSEL[1]
L
L
CC
supply to the processor must be turned off within 500 ms to
BSEL[0]
CC
H
H
, V
SS
, or to any other signal (including each other) can
CCP
BCLK Frequency
(1.05 V)—non C6 rail to ensure proper
133 MHz
100 MHz
SS
). Unused outputs can be left
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