AC80566UC005DE S LB2C Intel, AC80566UC005DE S LB2C Datasheet - Page 27

• Manufacturer Part Number: AC80566UC005DE S LB2C
• Description: MPU, ATOM PROCESSOR, Z510, U-FCBGA
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of AC80566UC005DE S LB2C

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 400MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 441
• Supply Voltage Range: 0.75V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications
3
3.1
3.2
Datasheet
Electrical Specifications
This chapter contains signal group descriptions, absolute maximum ratings, voltage
identification, and power sequencing. The chapter also includes DC specifications.
FSB, GTLREF, and CMREF
The processor supports two kinds of signalling protocol: Complementary Metal Oxide
Semiconductor (CMOS), and Advanced Gunning Transceiver Logic (AGTL+).
The “CMOS FSB” terminology used in this document refers to a hybrid signaling mode,
where data and address busses run in CMOS mode and strobe signals operate in GTL
mode. The reason to use GTL on strobe signals is to improve signal integrity.
The termination voltage level for the processor CMOS and AGTL+ signals is
V
integrity and platform design methods have become more critical than with previous
processor families.
The CMOS data and address busses require a reference voltage (CMREF) that is used
by the receivers to determine if a signal is a logical 0 or a logical 1. CMREF is only
applicable to data and address signals—not to the sideband signals listed in Table 5.
CMREF must be generated on the system board. In CMOS mode, there is no receiver-
side termination to I/O voltage (V
The AGTL+ inputs, including the sideband signals listed in Table 5, require a reference
voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or
a logical 1. GTLREF must be generated on the system board. Termination resistors are
provided on the processor silicon and are terminated to its I/O voltage (V
appropriate chipset will also provide on-die termination, thus eliminating the need to
terminate the bus on the system board for most AGTL+ signals.
The CMOS bus depends on reflected wave switching and the AGTL+ bus depends on
incident wave switching. Timing calculations for CMOS and AGTL+ signals are based
on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB,
including trace lengths, is highly recommended when designing a system.
Power and Ground Pins
For clean, on-chip power distribution, the processor will have a large number of VCC
(power) and VSS (ground) inputs. All power pins must be connected to V
planes while all VSS pins must be connected to system ground planes. Use of multiple
power and ground planes is recommended to reduce I*R drop. The processor VCC pins
must be supplied by the voltage determined by the VID (Voltage ID) pins.
CCP
= 1.05 V (nominal). Due to speed improvements to data and address bus, signal
CCP
).
CC
CCP
power
). The
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