AC80566UC005DE S LB2C Intel, AC80566UC005DE S LB2C Datasheet - Page 56

• Manufacturer Part Number: AC80566UC005DE S LB2C
• Description: MPU, ATOM PROCESSOR, Z510, U-FCBGA
• Manufacturer: Intel
• Series: ATOM - Z5xxr

Specifications of AC80566UC005DE S LB2C

• Core Size: 32bit
• Program Memory Size: 512KB
• Cpu Speed: 400MHz
• Digital Ic Case Style: FCBGA
• No. Of Pins: 441
• Supply Voltage Range: 0.75V To 1.1V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Table 15. Signal Description
Signal Description
A[31:3]#
A20M#
ADS#
ADSTB[1:0]#
BCLK[1:0]
BNR#
Signal Name
Type
I/O
I/O
I/O
I/O
I
I
A[31:3]# (Address) defines a 2
space. In subphase 1 (one) of the address phase, these pins
transmit the address of a transaction.
In sub-phase 2, these pins transmit transaction type information.
These signals must connect the appropriate pins of both agents
on the processor FSB. A[31:3]# are source synchronous signals
and are latched into the receiving buffers by ADSTB[1:0]#.
Address signals are used as straps which are sampled before
RESET# is de-asserted.
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address
wrap-around at the 1-MB boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to ensure
recognition of this signal following an input/output write
instruction, it must be valid along with the TRDY# assertion of
the corresponding input/output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus
agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal loop, or deferred
reply ID match operations associated with the new transaction.
Address strobes are used to latch A[31:3]# and REQ[4:0]# on
their rising and falling edges. Strobes are associated with signals
as shown below.
Signals
REQ[4:0]#, A[16:3]#
A[31:17]#
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All FSB agents must receive these signals to drive
their outputs and latch their inputs.
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing VCROSS.
BNR# (Block Next Request) is used to assert a bus stall by any
bus agent who is unable to accept new bus transactions. During
a bus stall, the current bus owner cannot issue any new
transactions.
Description
Associated Strobe
ADSTB[0]#
ADSTB[1]#
32
-byte physical memory address
Datasheet