SCANSTA101SM National Semiconductor, SCANSTA101SM Datasheet - Page 12

• Manufacturer Part Number: SCANSTA101SM
• Description: IC,Test/JTAG Support,CMOS,BGA,49PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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along with the corresponding load enable to set the bit in the
status register in the SIG. If the flag condition changes then
the clear for the corresponding bit is passed to the SIG to clear
the flag. The TDO_SM empty and the TDI_SM full flags are
passed to the SSI also. A counter enable is passed from the
SSI indicate to the FG when the SSI's pointer value has
changed. If a decrement and an increment occur at the same
time to either of the counters, the counter value will not
change.
PPI INTERFACE TIMING
The processor accesses to SCANSTA101 can be classified
into six categories:
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Register reads and register writes are performed the same
whether the device is in 16-bit mode or 32-bit mode. In 32-bit
mode, only the LS word is used. The MS word is ignored. All
timing for the 16-bit and 32-bit modes are exactly the same.
The 16-bit mode memory write is accomplished by performing
two consecutive register writes with the only difference being
that the actual write occurs on the second access. The 16-bit
mode register read consists of two accesses, with the first
access performed similar to the 16-bit register read but re-
quiring one more clock to complete the memory access. Since
all 32-bits of the memory data are captured on the first access,
the second memory read access is 2 clocks shorter than the
first.
The processor initiates a write cycle by asserting CE followed
by STB. A set time prior to asserting STB, the R/W is driven
low and the address and data buses are driven by valid ad-
dress and data, respectively. After edge detecting the STB
and registering all the inputs, the address is decoded to de-
termine which internal address within the STA101 will be
written by the processor. The DTACK will be asserted on the
same rising edge of SCK on which the STB's negative edge
is detected, indicating to the processor that it can deassert the
STB. When the STA101 detects the positive edge of the
STB, it will deassert the DTACK indicating to the processor
that it can start a new cycle. The processor can start a new
cycle by asserting the STB and by driving the address and
data buses with new address and data.
A read cycle is similar to the write cycle except that the
DTACK will not be asserted until the selected address
location's contents are loaded. So, for a 16-bit register read it
takes one more clock than it does for a write cycle.
Accesses to STA101 memory require two consecutive ac-
cesses in the 16-bit external bus mode. The memory writes
are similar to register writes but the only difference is that
processor has to perform two consecutive 16-bit writes to
write to the selected memory location. One important note,
during a memory read, is that DTACK is not asserted until the
contents of the memory is loaded into the capture registers.
For this reason the first read from the memory requires five
clocks which includes the memory access time, while the
second read is done in 3 clock cycles.
Serial Scan Interface
The Serial Scan Interface consists of the following units:
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register read
register write
16-bit memory read
16-bit memory write
32-bit memory read
32-bit memory write
Clock Divider and TCK_SM Control
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The clock divider unit divides system clock SCK based on the
programmable divisor set in the clock divider to generate
TCK_SM. The TCK_SM control unit gates TCK_SM if the
TDO_SM buffer is empty.
The TAP Tracker unit keeps track of the target's TAP con-
troller state. The purpose of the TAP Tracker is to determine
whether the target's TAP controller is in SIR or SDR state, so
that the necessary PAD bits are inserted.
The shifter block contains two 32-bit shift registers for
TDO_SM and TDI_SM respectively, and a 16-bit shift register
for TMS_SM.
The comparator unit compares the serial input on the TDI_SM
pin with the expected, data bit by bit, if the compare bit of the
Macro Structure is set. However, if compare/mask bit is set,
then the comparator unit compares only those bits that are
unmasked.
Expected and Mask Registers contain the data fetched from
the memory. This data will be used by the comparator to com-
pare the TDI_SM input with the expected data.
The SSIC provides the timing and control signals to synchro-
nize the operation of the various blocks in the SSI. The
ScanBridge Controller consists of the control logic to set up
the ScanBridge's hierarchy, if the ScanBridge Support Initi-
ate/Release bit is enabled, prior to scanning actual test vec-
tors out of TDO_SM.
CLOCK DIVIDER AND TCK_SM CONTROL
The clock divider will be a binary divider where only one bit of
the clock divider register will be set to one at any given time.
The implementation will ignore bits 0, and 8-15, so the sup-
ported divisors are 2, 4, 8, 16, 32, 64 and 128.
To generate a TCK_SM of frequency SCK/4, the clock divider
register should be set to 4 (00000100). This will enable the
gate at the output of bit 2 of the counter to generate a clock
of SCK divided by 4. If in LotF mode, then the TCK_SM enable
from the SSIC will gate TCK_SM when the TDO_SM buffer is
empty.
TAP TRACKER
The TAP Tracker consists of a 16-bit register to trace the IEEE
Standard 1149.1 state machine. The state machine is one hot
encoded and will continuously track the target's TAP Con-
troller based on the TMS_SM sequence. The TAP Tracker will
be used by the ScanBridge support controller to determine
whether the target's TAP controller is in SIR or SDR state so
that it can insert an appropriate number of pre and post-PAD
bits.
The TAP Tracker will enter Test-Logic Reset state upon set-
ting the TRST bit (bit 5) in the Setup register or by issuing a
sequence of five TMS_SM high bits.
TAP Tracker
Pointer Generator
Structure (Sequencer/Vector/Macro/ScanBridge)
Decoder
Structure (Sequencer/Vector/Macro/ScanBridge) Control
Registers
Count Generator
Shifter (TDO_SM/TDI_SM/TMS_SM)
Comparator
Expected and Mask Registers
Serial Scan Interface Controller (SSIC) and ScanBridge
Controller