SCANSTA101SM National Semiconductor, SCANSTA101SM Datasheet - Page 5

• Manufacturer Part Number: SCANSTA101SM
• Description: IC,Test/JTAG Support,CMOS,BGA,49PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PARALLEL PROCESSOR INTERFACE (PPI)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
S1
H1
D1
D1
D1
D1
D1
D1
D2
D2
D2
D2
D2
D2
D3
pHL1
W
MAX
RELEASE
Symbol
AC Electrical Characteristics/Operating Requirements
supply voltage and temperature ranges unless otherwise specified. C
Note 3: Due to uncertainty in the relationship of the STB placement to the system clock, SCK, the STB may be detected during the current or the next SCK cycle.
Note 4: An absolute maximum delay can be calculated as: (Max # SCK) x (SCK Period) + t
For example, for t
maximum delay is (3 x 100ns) + 11.5, or 311.5ns.
Set Up Time
CE, R/W, Addr, Data to STB
Hold Time
CE, R/W, Addr, Data to DTACK
Propagation Delay
STB low to DTACK low, Register Write
Propagation Delay
STB low to DTACK low, Register Read
Propagation Delay
STB low to DTACK low, Memory Write: 16-bit first
access
Propagation Delay
STB low to DTACK low, Memory Write: 16-bit second
access
Propagation Delay
STB low to DTACK low, Memory Read: 16-bit first
access
Propagation Delay
STB low to DTACK low, Memory Read: 16-bit second
access
Propagation Delay
STB high to DTACK TRISTATE, Register Write
Propagation Delay
STB high to DTACK TRISTATE, Register Read
Propagation Delay
STB high to DTACK TRISTATE, Memory Write: 16-bit
first access
Propagation Delay
STB high to DTACK TRISTATE, Memory Write: 16-bit
second access
Propagation Delay
STB high to DTACK TRISTATE, Memory Read: 16-bit
first access
Propagation Delay
STB high to DTACK TRISTATE, Memory Read: 16-bit
second access
Propagation Delay
Output data valid to DTACK low, all read cycles
Propagation Delay
STB low to INT low, register write (clears Interrupt)
Clock Pulse Width, SCK, H or L
Clock Frequency, SCK
Release Time, RST to STB
D1
(STB low to DTACK low, register write), the # SCK cycles is 2 or 3 and the delay, t
Parameter
5
Figures 11, 12
Figures 11, 12
Figure 11
Figure 12
Figure 11
Figure 11
Figure 12
Figure 12
Figure 11
Figure 12
Figure 11
Figure 11
Figure 12
Figure 12
Figure 12
Figure 11
Conditions
L
= 50 pF, R
D
.
L
D
= 500Ω unless otherwise specified.
, is 11.5ns. For a SCK with a 100ns period, the absolute
(Notes 3, 4)
# of SCK
9 or 10
2 or 3
4 or 5
3 or 4
7 or 8
3 or 4
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
5 or 6
1
2
Over recommended operating
Min
3.0
0
0
Max
11.5
11.5
11.5
11.5
11.5
11.5
10.0
10.0
10.0
10.0
10.0
10.0
10.5
66
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Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns