SCANSTA101SM National Semiconductor, SCANSTA101SM Datasheet - Page 28

• Manufacturer Part Number: SCANSTA101SM
• Description: IC,Test/JTAG Support,CMOS,BGA,49PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Note 23: LSB of the Clock Divider register is hard coded to zero.
Note 24: LSW LFSR Seed<15:0> is the LS word of the LFSR seed.
Note 25: This register along with register MSSEDR form a register pair and should be read/written with two consecutive read/write accesses.
Note 26: MSW LFSR Seed <15:0> is the MS word of the LFSR seed.
Note 27: This register along with register LSSEDR form a register pair and should be read/ written with two consecutive read/write accesses.
Note 28: LSW LFSR Result<15:0> is the LS word of the LFSR result.
Note 29: This register along with register MSRESR form a register pair and should be read/written with two consecutive read/write accesses.
Divisor<7:1>
LFSR Exponent<2:0>
'000'
'001'
'010'
'011'
Bit(s)
Bit(s)
Bit(s)
Bit(s)
Bit(s)
15:8
15:3
15:0
15:0
15:0
7:1
2:0
0
'0000000'
'0000001'
'0000010'
'0000100'
'0001000'
'0010000'
'0100000'
'1000000'
Type
Type
Type
Type
Type
RW
RW
RW
RW
RW
RO
RO
RO
TABLE 28. TDI_SM LFSR LSB Result Register (LSRESR) ($0A) (Notes 28, 29)
TABLE 27. TDI_SM LFSR MSB Seed Register (MSSEDR) ($09) (Notes 26, 27)
TABLE 26. TDI_SM LFSR LSB Seed Register (LSSEDR) ($08) (Notes 24, 25)
Reserved
Divisor
Reserved (hard coded) (Note 23)
Reserved
LFSR
LSW LFSR Seed
MSW LFSR Seed
LSW LFSR Result
TABLE 25. TDI_SM LFSR Exponent Register (EXPR) ($07)
Clock divisor for the division of the SCK clock to the serial scan clock.
No serial scan clock generated.
Divide SCK by 2
Divide SCK by 4
Divide SCK by 8
Divide SCK by 16
Divide SCK by 32
Divide SCK by 64
Divide SCK by 128
LFSR exponent. Binary encoding for the selection between three polynomials.
No polynomial selected
Polynomial 1: X
Polynomial 2: X
Polynomial 3: X
TABLE 24. Clock Divider Register (CLKDIV) ($05)
Field
Field
Field
Field
Field
32
32
32
+ X
+ X
+ X
7
28
7
+ X
+ X
+ X
28
5
6
27
+ X
+ X
+ X + 1
3
2
+ X
+ 1
Address Offset
Address Offset
Address Offset
Address Offset
Address Offset
2
+ X + 1
0
0
0
0
0
0
0
0
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
0000h
0000h
0000h
0000h
000b
00h
00h
0b
Reset Source
Reset Source
Reset Source
Reset Source
Reset Source
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST