SCANSTA101SM National Semiconductor, SCANSTA101SM Datasheet - Page 2

• Manufacturer Part Number: SCANSTA101SM
• Description: IC,Test/JTAG Support,CMOS,BGA,49PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

www.national.com
Interface
Parallel Processor Interface
Serial Scan Interface
Test and Debug Interface
System Inputs
Figure 1 shows a high level view of the SCANSTA101 Scan
Master and its interface groups. Table 1 provides a brief de-
scription of each of these interface groups. Table 2 provides
a brief description of the external interfaces. The device is
composed of three interfaces around a dual-port memory.
These interfaces consist of the Parallel Processor Interface
Connection Diagram
Description
Used for configuration, ScanMaster scan chain loads and reads, programmable device file
loads and reads, and status monitoring.
Performs parallel to serial conversion, sequences and formats the outgoing serial stream to
conform to 1149.1 protocol.
Interfaces used for manufacturing tests, this includes a JTAG interface and a scan interface.
The three scan interface pins are shared with three of the data pins.
Interface inputs for system control, i.e. clock, reset and output tristate control.
TABLE 1. Interface Descriptions
BGA Package Pinout
(Top View)
2
(PPI), Serial Scan Interface (SSI), and Test and Debug Inter-
face. The System Input block is included only to designate
inputs that have global use across the device. The Test and
Debug interface supports BIST, boundary scan, and internal
scan for this device.
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