SCANSTA101SM National Semiconductor, SCANSTA101SM Datasheet - Page 23

• Manufacturer Part Number: SCANSTA101SM
• Description: IC,Test/JTAG Support,CMOS,BGA,49PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

REGISTER DEFINITIONS
The following sections include descriptions of each address-
able register in the ScanMaster memory space. Following the
title of the particular register, the mnemonic for the register is
Note 11: Reserved Use Vector x for future growth for the number of vectors.
Onboard Memory BIST
Use Sequencer
Use Vector <2:0>
Bit(s)
15:14
12:9
7:3
2:0
13
8
'000'
'001'
'010'
'011'
'100'
'1'
'0'
'1'
'0'
Type
RW
RW
RW
RO
RO
RO
Reserved
Onboard Memory BIST
Reserved
Use Sequencer
Reserved Use Vector x (Note 11)
Use Vector x
ScanMaster memory BIST enable. This bit is self clearing when BIST result is written to
the Memory BIST Result bit in the Status register.
Initiate on chip memory BIST
On chip memory BIST complete
Sequencer enable/disable (For preloaded vectors only)
Enable sequencer
Disable sequencer
Use Vector x designates the vector "x" which is enabled, where "x" is the vector number,
a binary encoding of bits <2:0>. Only vectors 1 through 4 are valid. Vectors 5 through 7
reserved for future use.
No vector enabled
Vector 1 enabled
Vector 2 enabled
Vector 3 enabled
Vector 4 enabled
TABLE 19. Start Register (START) ($00)
Field
23
included in parentheses as well as the physical address lo-
cation in hexadecimal notation (value preceded by $). KEY-
RO: Read Only; RW: Read/Write.
Address Offset
0
0
0
0
0
0
Reset Value
0000b
0000h
000b
00b
0b
0b
Reset Source
SYS_RST
SYS_RST
SYS_RST
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