SCANSTA101SM National Semiconductor, SCANSTA101SM Datasheet - Page 19

• Manufacturer Part Number: SCANSTA101SM
• Description: IC,Test/JTAG Support,CMOS,BGA,49PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SETUP[11:10]
00
01 or 10
11
Signal Name
SCK
RST
OE
Signal Name
DATA(31:16)
DATA(15:0)
ADDRESS(4:0)
CE
R/W
STB
DTACK
INT
Note 10: Default TDO value (bit 6 of the SETUP register) may be set to a 0 when SETUP[11:10]=01 and to a 1 when SETUP[11:10]=10.
For BIST and STATE macros, the TDO_SM output behaves
exactly as shown in the above table, however, for the shift
macros, with or without capture, the TDO_SM output behaves
as per the table only when the corresponding TMS_SM output
is not driven by the macro structure bit 7 or 8. On each falling
edge of the TCK_SM following the TCK_SM's falling edge on
which the TMS_SM changes state from bit 6 of the macro
structure to the bit 7of the macro structure, the serial test vec-
Hardware Interface Details
No. of
No. of
Bits
Bits
16
16
1
1
1
5
1
1
1
1
1
TDO_SM
Hold Previous value
Default TDO value (Bit 6 of the SETUP register) (Note 10)
High Impedance
Pin Type
Pin Type
I,H
I/O
I/O
O
O
I
I
I
I
I
I
TABLE 15. Parallel Processor Interface Signal Descriptions
LVTTL (weakest
TABLE 14. System Interface Signal Description
Driver Type
Driver Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
driver)
TABLE 13. TDO_SM Output Behavior
O/D
Freq.
Freq.
MHz
MHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
66
19
tor data fetched from the memory will be presented on the
TDO_SM output. On the falling edge of the TCK_SM on which
the final bit of the test vector is presented on the TDO_SM
output, the TMS_SM will be presented with the macro struc-
ture bit 8. On the consequent TCK_SM falling edges and on
the TCK_SM falling edges before the TMS_SM changes state
from bit 6 to bit 7 of the macro structure the TDO_SM will
behave as per the table above.
Description
System Clock: This is the main clock signal to the STA101. SCK
is used to clock all internal circuitry
Hardware Reset signal (with hysteresis (H)): This is the STA101
asynchronous reset signal.This signal resets the entire STA101
and sets all registers to their respective default values.
Output enable: Tristates all dot1 outputs when high.
Description
Bidirectional Data Bus. Not bonded out in packaged part. These
are only used in the 32-bit macro version.
Bidirectional Data Bus.
Address Bus
Chip Enable, when low, enables the PPI for transfers. DATA
(31:0) and DTACK are tristated when CE is high.
Read/Write defines a PPI cycle. Read when high, write when
low.
Strobe is used for timing all PPI transfers. DATA(31:0) are
tristated when STB is high. Data valid setup is with respect to
the falling edge of STB and data valid hold is with respect to
rising edge of STB.
Data Acknowledge (open drain - sustained tristate). DTACK is
used to synchronize asynchronous transfers between the host
and the STA101. During write cycles, DTACK goes low when
data has been registered and then goes to high impedance
when the cycle has been completed. During read cycles
DTACK goes low when data bus is driven with the valid data
and then goes to high impedance when the cycle has been
completed.
Interrupt is used to trigger a host interrupt for any of the defined
interrupt events. Signal is active high.
www.national.com