SCANSTA101SM National Semiconductor, SCANSTA101SM Datasheet - Page 15

• Manufacturer Part Number: SCANSTA101SM
• Description: IC,Test/JTAG Support,CMOS,BGA,49PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Compare
0
0
1
1
Results of Compare bit (bit 15 of Status register) stores the
comparison results in the status register. This bit defaults to
fail (zero) and will be updated only after the current vector is
processed. In the case of a single vector the Results of Com-
pare bit will be set to one (pass) only if all the bits in the
scanned in vector match the expected vector. However, in the
case of the sequencer only the results of final vector compar-
ison will be taken into account.
After reset and before every sequencer process, flip-flops 1
and 3 are initialized to zero while flip-flop 2 is set to 1. When
the compare feature is enabled flip-flop 1 is continuously up-
dated with the immediate comparison results (1 for pass and
0 for fail). Flip-flop 2 is reset to zero when a mismatch occurs
and remains in this state for the remainder of the current vec-
tor processing. When the current vector is completely pro-
cessed flip-flop 3 (Results of Compare register) will be
updated with the current status.
SERIAL SCAN INTERFACE CONTROLLER AND
SCANBRIDGE CONTROLLER
The Serial Scan Interface Controller (SSIC) remains in the
Idle state until new data are written to the Start register. When
this event occurs the following operations are performed:
1.
If the ScanBridge Support Initiate/Release bit was not set
previously and is currently set in the Setup register, the
SSIC initializes the ScanBridge Controller (SBC) to
perform the following steps to set up all ScanBridges in
the hierarchy.
1.
Determine the number of levels of ScanBridge
support to be inserted (from the ScanBridge support
structure)
TABLE 12. Compare and Use Mask/Compare Bit Descriptions
Use Mask/Compare
0
1
0
1
FIGURE 6. Compare Logic
15
Each vector within the sequencer is repeated until the vector
repeat count is exhausted. However, the sequence is repeat-
ed until either the sequencer repeat count is exhausted or the
compare passes and that the loop of the sequence is com-
pleted.
Figure 6 illustrates the compare logic.
2.
3.
4.
5.
6.
Sequence TMS_SM so that all ScanBridges in the
same level of hierarchy enter the SIR state, and then
shift in the address (from the ScanBridge structure)
to select a ScanBridge in the current level of
hierarchy. The ScanBridge's TAP controller is then
sequenced through the Update-IR state.
Sequence TMS_SM so that the selected
ScanBridge's TAP controller enters the SIR state,
then scan in the MODESEL instruction to put its
mode register in the data path.
Sequence the selected ScanBridge's TAP controller
to enter the Shift-DR state and scan in the LSP
contents (from the ScanBridge structure) into its
mode register. The ScanBridge's TAP controller is
then sequenced through the Update-DR state.
Repeat Step 1c, but this time scan in the UNPARK
instruction so that the LSP is inserted into the active
scan chain.
Sequence the ScanBridge's TAP controller to enter
the RTI state (the LSP will not be unparked until its
TAP controller enters RTI).
Description
Do Not Compare
Compare with Mask
Compare without Mask
Compare with Mask
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