SCANSTA101SM National Semiconductor, SCANSTA101SM Datasheet - Page 3

• Manufacturer Part Number: SCANSTA101SM
• Description: IC,Test/JTAG Support,CMOS,BGA,49PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

VCC
GND
D(15:0)
D(31:16)
(Note 1)
A(4:0)
SCK
INT
OE
DTACK
R/W
STB
CE
RST
TDO
TDI
TMS
TCK
TRST
TDI_SM
TDO_SM
TMS_SM
TCK_SM
TRST0_SM
TRST1_SM
(Note 1)
TRIST_SM
TABLE 2. Pin Descriptions
Note 1: D(31:16) in the Parallel Processor Interface and TRST1_SM in the Serial Scan Interface are not bonded out for the packaged part. These are used in
the 32-bit Macro Mode only.
Name
Pin
No. Pins
16
16
4
4
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N/A
N/A
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Power
Ground
Bidirectional Data Bus. Signals are bonded out for the packaged device. D15 and D14
are shared pins with SCAN_IN, and SCAN_OUT respectively.
Bidirectional Data Bus. These signals are not available in the packaged device.
Address Bus
The system clock that drives all internal timing. TCK_SM is a gated, divided and buffered
version of SCK.
Interrupt Output
Output enable that tristates all 1149.1 "_SM" outputs when high.
DTACK is used to synchronize asynchronous transfers between the host and the
STA101. When CE is high, DTACK is tristated. When CE is low, DTACK is enabled.
DTACK goes low when data has been registered and then goes tri-state when the cycle
has completed.
R/W defines a PPI cycle. Read when high, write when low.
Strobe is used for timing all PPI transfers. D(15:0), or D(31:0) in 32-bit mode, are
tristated when STB is high. Data valid setup is with respect to the falling edge of STB
and data valid hold is with respect to rising edge of STB.
Chip Enable, when low, enables the PPI for data transfers. CE can remain low during
back-to-back accesses. D(15:0), or D(31:0) in 32-bit mode, and DTACK are tristated
when CE is high.
Asynchronous reset, when low, initializes the STA101.
Test Data Out is the serial scan output from the STA101. TDO is enabled when OE is
low.
Test Data In is the serial scan input to the STA101.
Test Mode Select. The Test Mode Select pin is a serial input used to accept control logic
to the Test & debug interface.
Test Clock Input for 1149.1
Test Reset. This pin should be tied to ground by a 1K resistor to hold the Test and Debug
Interface in the Test-Logic-Reset state during device power-up. This avoids invalid
states when ramping supply voltages.
Scan Master Test Data Input in the Serial Scan Interface
Scan Master Test Data Output in the Serial Scan Interface
Scan Master Test Mode Select in the Serial Scan Interface
Scan Master Test Clock in the Serial Scan Interface
Scan Master Test Reset output in the Serial Scan Interface
Redundent ScanMaster TRST. This signal is not available for the packaged device.
The TRI-STATE notification pin exerts a high signal when TDO_SM is TRI-STATED
3
Description
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