IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 137

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Target Write Transactions
This section describes the behavior of the PCI MegaCore functions in the
following types of target write transactions:
■
■
■
Memory Write Transactions
The PCI MegaCore functions support the following types of matched bus
width and mismatched bus width memory write transactions in target
mode:
■
■
■
1
For all memory write transactions, the following sequence of events is the
same:
1.
2.
3.
4.
Memory write
I/O write
Configuration write
Single-cycle memory write
Burst memory write
Mismatched bus width memory write
The address phase occurs when the PCI master asserts framen (and
req64n in the case of a 64-bit transaction) and drives the address on
ad[31..0] and the command on cben[3..0]. Asserting req64n
indicates to the target device that the master device is requesting a
64-bit data transaction.
If the address of the transaction matches the memory range
specified in a base address register, the PCI MegaCore function
turns on the drivers for the ad bus, devseln, trdyn, stopn, and
par (as well as par64 and ack64n for 64-bit transactions) in the
following clock cycle.
The PCI MegaCore function drives and asserts devseln (and
ack64n for 64-bit transactions) to indicate to the master device that
it is accepting the transaction.
One or more data phases follow, depending on the type of write
transaction.
Mismatched bus-width transactions are 32-bit PCI transactions
performed by the pci_mt64 and pci_t64 MegaCore
functions.
PCI Compiler Version 10.1
Functional Description
3–63