IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 302

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Master Operation
7–34
PCI Compiler User Guide
PCI target disconnect
PCI target retry
PCI target-abort
PCI master-abort
Termination Condition
Table 7–11. PCI Master Read Request Termination Conditions (Part 2 of 2)
The continuation of the PCI read is requested from the master controller arbiter.
PCI interrupt status register ERR_PCI_READ_FAILURE (bit 1) is set to 1. Dummy data
is returned to complete the Avalon-MM read request. The next operation is then
attempted in a normal fashion.
Arbitration Among Pending PCI Master Requests
The transaction arbiter is responsible for managing all pending PCI
master requests. To manage the continuos cycle of requests, the
transaction arbiter uses priority guidelines to determine which master
request to service first. This section discusses how a master request is
issued as well as the transaction arbiter’s priority guidelines.
A PCI master request can be issued via any of the following:
■
■
■
Figure 7–8 on page 7–27
from the pending read queue (i.e., for read requests), or directly from the
command/data buffer (i.e., for write requests). The transaction arbiter
selects one of the "eligible" commands to service. In the Avalon-to-PCI
command/data buffer, only the head-of-line command can be eligible.
PCI write and read command eligibility are defined below:
■
■
Continuation of a previously interrupted command
A new read from the Avalon-to-PCI bypassable read buffer
A new write command from the Avalon-to-PCI command/write
data buffer
PCI write commands are "eligible" if either:
●
●
PCI read commands are "eligible" if:
●
●
There are eight data phases of data
There is enough data in the Avalon-to-PCI command/write
data buffer to satisfy the remaining burst count
They have already been assigned to an Avalon-to-PCI read
response buffer
They have not been assigned and there is an Avalon-to-PCI read
response buffer available
PCI Compiler Version 10.1
shows that a command can be serviced either
Resulting Action
Altera Corporation
January 2011