IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 318

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Control & Status Registers
7–50
PCI Compiler User Guide
0
1
2
6:3
7
8
9
Table 7–18. PCI Interrupt Status Register – Address: 0x0040 (Part 1 of 2)
Bit
ERR_PCI_WRITE_FAILURE
ERR_PCI_READ_FAILURE
ERR_NONP_DATA_DISCARD
Reserved
AV_IRQ_ASSERTED
PCI_PERR_REP
PCI_TABORT_SIG
Name
Table 7–18
status of all conditions that can cause the assertion of a PCI interrupt.
PCI Compiler Version 10.1
RW1C
RW1C
RW1C
N/A
RO
RO
RO
describes the PCI interrupt status register, which shows the
Access
Mode
When set to 1 indicates a write to PCI failure (abort or
retry threshold exceeded). This bit can also be cleared
by writing a '1' to the same bit in the Avalon-MM
interrupt status register.
This bit will only be implemented if the bridge is either
operating in the PCI Master/Target Peripheral or PCI
Host-Bridge Device mode.
When set to 1 indicates a read from PCI failure (abort
or retry threshold exceeded). This bit can also be
cleared by writing a '1' to the same bit in the
Avalon-MM interrupt status register.
This bit will only be implemented if the bridge is either
operating in the PCI Master/Target Peripheral or PCI
Host-Bridge Device mode.
When set to 1 indicates non-prefetchable data read
from Avalon-MM was discarded because the PCI read
request was not retried before the discard timer
expired. Note that this bit can also be cleared by a write
of a '1' to the same bit in the Avalon-MM interrupt status
register.
This bit will only be implemented when the
non-prefetchable Avalon-MM master port is
implemented.
Current value of the Avalon-MM interrupt (
port to the non-prefetchable Avalon-MM master port
(or prefetchable Avalon-MM master port if the
non-prefetchable port is not used).
0 – Avalon
1 – Avalon
Reflects the current value of PCI status register bit 8,
PERR
direct access to the PCI configuration status register.
Reflects the current value of PCI status register bit 11,
target abort signaled. This bit can only be cleared
through a direct access to the PCI configuration status
register. Because the PCI-Avalon bridge does not
signal target abort, this bit is never set.
reported. This bit can only be cleared through a
IRQ
IRQ
is not being signaled.
is being signaled.
Description
Altera Corporation
January 2011
IRQ
) input