IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 215

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Note to
(1)
mstr_tranx
trgt_tranx
trgt_tranx_mem_init.dat
altera_tb
run_altera_modelsim.tcl
run_modelsim.tcl
run_vcs.sh
run_ncverilog.sh
Table 4–3. Files Contained in the example Directory
This file is provided in both VHDL and Verilog HDL.
Table
(1)
(1)
(1)
4–3:
File
(1)
Refer to
modified testbench files.
“Simulation Flow” on page 4–20
This module contains the master transactor code. The INITIALIZATION
section has the parameters set to simulate the Local Reference Design.
The USER COMMANDS section has the PCI commands that will be
executed during simulation.
This module contains the target transactor code. The address_lines and
mem_hit_range settings are set to simulate the reference design.
This file is the memory initialization file for the target transactor.
This top-level file instantiates the testbench module files, the
IP functional simulation model of the
and the reference design file. The
MegaCore function is connected to address bit 28 and the
of the target transactor is connected to address bit 29.
This script can be used with the Altera-ModelSim simulator. This script
compiles all the files provided in <path>\pci_compiler
\megawizard_flow\testbench\<HDL language>
\<PCI MegaCore function>\example and simulates the reference
design for the transactions specified in the mstr_tranx file.
This script can be used with the ModelSim SE, PE or AE simulators.
This script compiles all the files provided in <path>\pci_compiler
\megawizard_flow\testbench\<HDL language>
\<PCI MegaCore function>\example and simulates the reference
design for the transactions specified in the mstr_tranx file.
This script is used with VCS simulator. This script compiles the files
provided in <path>\pci_compiler\megawizard_flow
\testbench\<HDL language>\<PCI MegaCore function>
\example\<function> and simulates the reference design for the
transactions specified in the mstr_tranx file.
This script must be used with NC-Verilog simulator. This script will
compile all the files provided in <path>\pci_compiler
\megawizard_flow\testbench\<HDL language>
\<PCI MegaCore function>\example and simulates the reference
design for the transactions specified in the mstr_tranx file.
PCI Compiler Version 10.1
Modified Testbench Files
Top-level Design File
Simulation Scripts
Description
idsel
for more information on the
pci_mt64
signal of the Altera PCI
PCI Compiler User Guide
MegaCore function,
idsel
Testbench
signal
4–5