IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 283

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Bus
Commands
PCI Target
Operation
Altera Corporation
January 2011
Notes to
(1)
(2)
(3)
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
Table 7–3. PCI Bus Command Support Summary
Command Value
Refers to the ability of the PCI-Avalon bridge to initiate a PCI transaction with the indicated command.
Refers to the ability of the PCI-Avalon bridge to accept a PCI transaction with the indicated command.
This command is not supported in 32-bit PCI bus width applications.
Table
7–3:
Interrupt acknowledge
Special cycle
I/O read
I/O write
Reserved
Reserved
Memory read
Memory write
Reserved
Reserved
Configuration read
Configuration write
Memory read multiple
Dual address cycle (DAC)
Memory read line
Memory write and invalidate
Bus Command Cycle
Table 7–3
The bus commands are discussed in greater detail in
Operation” on page 7–15
Because it is used with all device types, the PCI target mode is the most
basic operational mode for the PCI-Avalon bridge. In PCI target mode,
the PCI-Avalon bridge supports the following PCI bus transactions:
■
■
■
Memory read/write
Configuration read/write
IO read/write
shows the PCI bus commands support for PCI-Avalon bridge.
PCI Compiler Version 10.1
No
No
Yes
Yes
Ignored
Ignored
Yes
Yes
Ignored
Ignored
Yes
Yes
Yes
Yes
Yes
No
and
(3)
PCI Master
“PCI Master Operation” on page
(1)
Ignored
Ignored
Yes
Yes
Ignored
Ignored
Yes
Yes
Ignored
Ignored
Yes
Yes
Yes
Yes
Yes
Yes
Functional Description
(3)
“PCI Target
PCI Target
7–27.
(2)
7–15