IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 60
IPR-PCI/T32
Manufacturer Part Number
IPR-PCI/T32
Description
IP CORE Renewal Of IP-PCI/T32
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/T32
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Target, 32 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 60 of 358
- Download datasheet (3Mb)
Read-Only PCI Configuration Registers
Read-Only PCI
Configuration
Registers
PCI Base
Address
Registers
(BARs)
2–2
PCI Compiler User Guide
Parameters for read-only PCI configuration space registers are defined on
the Read-Only PCI Configuration Registers page of the Parameterize -
PCI Compiler wizard.
The following read-only PCI configuration space register parameters are
set on this page:
■
■
■
■
■
■
■
■
The parameters require hexadecimal values. For information on the
functionality of the read-only registers, refer to
on page
The PCI MegaCore functions implement up to six 32-bit BARs and an
expansion ROM BAR. The pci_mt64 and pci_t64 MegaCore functions
can also implement one 64-bit BAR using either BAR 1 and BAR0, or
BAR2 and BAR1.
You must instantiate at least one BAR in your application design.
Multiple BARs must be implemented in sequence starting from BAR0. By
default, BAR0 is enabled and reserves 1 MByte of memory space.
In addition to allowing normal BAR operation where the system writes
the base address value during system initialization, the PCI MegaCore
functions allow the base address of any BAR to be hardwired using the
Hardwire BAR option. When hardwiring a BAR, the BAR address
becomes a read-only value supplied to the PCI MegaCore function
through the parameter value. System software cannot overwrite a base
address register that is hardwired. The value provided for the hardwired
BAR is written into the BAR, including the four least significant bits.
Thus, you must provide the appropriate value for all of the contents of the
BAR.
1
The PCI BAR attributes are defined on the Base Address Registers
(BARs) page of the Parameterize - PCI Compiler wizard.
Device ID
Vendor ID
Revision ID
Subsystem ID
Subsystem Vendor ID
Minimum Grant
Maximum Latency
Class Code
3–28.
Use hardwired BARs in closed systems only.
PCI Compiler Version 10.1
“Configuration Registers”
Altera Corporation
January 2011
Related parts for IPR-PCI/T32
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/1
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/4
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/8
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP NIOS II MEGACORE RENEW
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-XAUIPCS
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: