IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 185

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
1
2
3
5
Table 3–39. Zero-Wait State Burst Memory Write Master Transaction (Part 1 of 3)
Clock
Cycle
The local side asserts
The function outputs
function asserts
PCI bus.
The PCI bus arbiter asserts
that the grant occurs immediately and the PCI bus is idle at the time gntn is asserted, this action
may not occur immediately in a real transaction. Before the function proceeds, it waits for
asserted and the PCI bus to be idle. A PCI bus idle state occurs when both
deasserted.
The function turns on its output drivers, getting ready to begin the address phase.
The function also outputs
request. During this same clock cycle, the local side should provide the PCI address on
l_adi[31..0]
The local side master interface asserts
side. The function does not assert
that it is ready to send data, only for the first data phase on the local side. For subsequent data
phases, the PCI MegaCore function asserts
The PCI MegaCore function continues to assert its
The function also asserts
lm_tsr[0]
and the PCI command on
Table 3–39
memory write master transaction. The 64-bit extension signals are not
applicable to the pci_mt32 function.
reqn
lm_req64n
lm_tsr[1]
lm_adr_ackn
to the PCI bus arbiter to request bus ownership. At the same time, the
gntn
PCI Compiler Version 10.1
to indicate to the local side that the master is requesting control of the
shows the sequence of events for a 64-bit zero-wait state burst
to grant the PCI bus to the function. Although
irdyn
to request a 64-bit transaction.
to indicate to the local side that the PCI bus has been granted.
lm_rdyn
to indicate to the local side that it has acknowledged its
regardless if the local side asserts
l_cbeni[3..0]
irdyn
Event
to indicate that it is ready to send data to the PCI
reqn
if the local side is ready to send data.
signal until the end of the address phase.
.
framen
Functional Description
lm_rdyn
Figure 3–31
and
gntn
irdyn
to indicate
shows
3–111
to be
are