IPR-PCI/T32 Altera, IPR-PCI/T32 Datasheet - Page 73

• Manufacturer Part Number: IPR-PCI/T32
• Description: IP CORE Renewal Of IP-PCI/T32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/T32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Note to
(1)
17
31..18
Number
Table 2–2. Bit Definition of the ENABLE_BITS Parameter (Part 5 of 5)
Bit
These parameters affect master functionality and therefore only affect the pci_mt64 and pci_mt32 MegaCore
functions.
Table
MW_CBEN_ENA
Reserved
2–2:
Bit Name
PCI Compiler Version 10.1
0
0
Default
Value
In a standard master burst transaction the byte
enables accompanying the initial data word
provided by the local side are used throughout the
master burst transaction. Turning on Allow
Variable Byte Enables During Burst
Transactions allows byte enables to change for
successive data words during the transaction.
This option affects both burst memory read and
burst memory write master transactions.
However, use this option only for burst memory
write master transactions. Refer to
Write Master Transaction with Variable Byte
Enables” on page 3–119
For burst memory read master transactions, you
must keep the byte enables constant throughout
the transaction. Typically the byte enable values
are set to 0 for bust memory read master
transactions.
Reserved.
Definition
for more information.
Parameter Settings
“Burst Memory
2–15