IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 108

• Manufacturer Part Number: IPTR-C2H-NIOS
• Description: IP CORE Renewal Of IPT-C2H-NIOS
• Manufacturer: Altera

Specifications of IPTR-C2H-NIOS

• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: Nios II
• Features: ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Performance
Figure 4–6. CRC Critical Path Scheduling by Assignment
4–14
Nios II C2H Compiler User Guide
Iteration
Loop
0
1
2
Time 
13:lut_addr=((crc&0xFF)^
0
State(0
2
*data++;

6)
4
soon as the previous execution is complete. Not surprisingly, the critical
path statement is what limits the speed of the loop, and hence what
determines CPLI.
Notice, also, that line 13 (lut_addr = (crc & 0xFF) ^ *data++)
appears to take more clock cycles than line 14 (crc = (crc >> 8) ^
table[lut_addr]). The C2H Compiler “stretches out” the calculation
of lut_addr so that it is available exactly when it is needed. The memory
access in line 14 is nonetheless the limiting operation.
Scheduling Information
There are two ways of presenting the loop scheduling information: per
assignment, and per state.
13:lut_addr=((crc&0xFF)^
6
14:crc=((crc>>8)^
table[lut_addr];
State(6
State(0
8
*data++;

11)

10
6)
9.1
13:lut_addr=((crc&0xFF)^
12
14:crc=((crc>>8)^
table[lut_addr];
State(6
14
State(0
*data++;

11)

16
6)
13:lut_addr=((crc&0xFF)^
18
14:crc=((crc>>8)^
table[lut_addr];
State(6
State(0
20
*data++;
Altera Corporation

11)

November 2009
6)
22
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