IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 45

• Manufacturer Part Number: IPTR-C2H-NIOS
• Description: IP CORE Renewal Of IPT-C2H-NIOS
• Manufacturer: Altera

Specifications of IPTR-C2H-NIOS

• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: Nios II
• Features: ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Figure 3–3. Two Stages of Pipelined Multiplication Operators
Altera Corporation
November 2009
Figure 3–1
Figure 3–2. Pipelined Multiplication Operator
Figure 3–2
Iteration Statements
An iteration statement (do, for, or while), also known as a loop
statement, translates to a finite state machine in hardware. The state
machine controls execution of all the statements inside the loop block. A
loop inhibits (stalls) its parent state machine. In other words, if a loop
exists within an outer loop, the state machine for the outer loop stalls each
iteration and waits for the inner loop state machine to complete.
int foo = a * b + x;
int bar = a * b * c + x;
shows the hardware that results from the following statement:
shows the hardware that results from the following statement:
9.1
C-to-Hardware Mapping Reference
Nios II C2H Compiler User Guide
3–5