IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 64
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
IPTR-C2H-NIOS
Manufacturer Part Number
IPTR-C2H-NIOS
Description
IP CORE Renewal Of IPT-C2H-NIOS
Manufacturer
Altera
Datasheet
1.IPT-C2H-NIOS.pdf
(138 pages)
Specifications of IPTR-C2H-NIOS
Software Application
IP CORE, NIOS Processor And Functions
Core Architecture
Nios II
Features
ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
Core Sub-architecture
Cyclone
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
- Current page: 64 of 138
- Download datasheet (911Kb)
Memory Accesses
3–24
Nios II C2H Compiler User Guide
Specifying Master-Slave Connections
By default, the C2H Compiler connects all master ports of an accelerator
to all the memory slave ports that the CPU data master port connects to.
These default connections guarantee that the accelerator can access any
memory addresses that the processor can access. However, master-slave
connections have an associated hardware resource cost. The extra
multiplexing and arbitration logic associated with a master-slave
connection often reduces the maximum achievable frequency (f
the system. If an accelerated function, by design, does not ever access
certain memories, you can eliminate the connection to the slave memory
to save resources and improve f
The C2H Compiler provides a connection pragma that associates a
pointer variable with an Avalon-MM slave port, which is typically a
memory. A pointer variable can translate to one or more master ports,
depending on how many times it is dereferenced in the C code. The
connection pragma directs the C2H Compiler to connect all master ports
generated for a particular variable to a specific slave port in the SOPC
Builder system.
The connection pragma is defined as follows:
The connection pragma must be placed outside the function to accelerate
in the same file. <function name> and <variable name> are the exact names
of the accelerated function and the pointer variable. <module> is the exact
name of the component instance, as specified in SOPC Builder.
<slave name> is optional. If <slave name> is provided, it is the exact name
of a specific slave port on <module>. If the module only contains one slave,
you can omit <slave name>. However, if you omit <slave name> when the
module contains multiple slaves, the compiler issues an error.
To connect a variable's master ports to multiple slave ports, you can use
multiple pragmas. If you use the connection pragma for a specific
variable, the C2H Compiler connects only the slave ports specified in
pragma statements.
In addition to reducing arbitration logic, the connection pragma helps the
C2H Compiler determine if two pointers overlap. If the memory
connections for two separate variables are mutually exclusive, the
compiler concludes that the pointers are never dependent on each other.
For more information, refer to section
#pragma altera_accelerate connect_variable \
<function name>/<variable name> to <module>[/<slave name>]
9.1
MAX
.
“Pointer Aliasing” on page
Altera Corporation
November 2009
MAX
3–32.
) of
Related parts for IPTR-C2H-NIOS
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![IPTR-DSPBUILDER](/photos/39/51/395153/4696159_tmb.jpg)
Part Number:
Description:
DSP BUILDER SOFTWARE
Manufacturer:
Altera
Datasheet:
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: