IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 60

• Manufacturer Part Number: IPTR-C2H-NIOS
• Description: IP CORE Renewal Of IPT-C2H-NIOS
• Manufacturer: Altera

Specifications of IPTR-C2H-NIOS

• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: Nios II
• Features: ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Memory Accesses
Example 3–13. volatile Type Qualifier
volatile char *DataFIFO = FIFO_BASE;
char Byte0 = *DataFIFO;
char Byte1 = *DataFIFO;
char Byte2 = *DataFIFO;
char Byte3 = *DataFIFO;
Example 3–14. Equivalent Pointers
char *DataFIFO = FIFO_BASE;
char Byte0 = *DataFIFO;
char Byte1 = *DataFIFO;
char Byte2 = *DataFIFO;
char Byte3 = *DataFIFO;
// The code above is equivalent to the following:
char *DataFIFO = FIFO_BASE;
char dereferenced_DataFIFO = *DataFIFO;
char Byte0 = dereferenced_DataFIFO;
char Byte1 = dereferenced_DataFIFO;
char Byte2 = dereferenced_DataFIFO;
char Byte3 = dereferenced_DataFIFO;
3–20
Nios II C2H Compiler User Guide
Example 3–13
distinct reads from a constant address.
By comparison,
equivalent, due to the consolidation of equivalent pointers. In this case,
the type of *DataFIFO is not declared volatile.
Avalon-MM Master Port Signal Generation
A dereference operation, such as *(ptr_to_int + i), translates to an
Avalon-MM master port on the accelerator. This section describes how
hardware accelerator logic generates the signals that drive the master
port.
Avalon-MM master ports created by the C2H Compiler comprise the
following fundamental elements:
■
■
■
Logic to compute the address signal
For write transfers only, logic to compute the write-data signal
Logic to control the read-enable or write-enable signal
demonstrates the use of volatile to guarantee multiple,
Example 3–14
9.1
demonstrates two sections of code that are
Altera Corporation
November 2009