AD9522-1BCPZ-REEL7 Analog Devices Inc, AD9522-1BCPZ-REEL7 Datasheet - Page 23

12- Channel Clock Generator W/Int VCO

AD9522-1BCPZ-REEL7

Manufacturer Part Number
AD9522-1BCPZ-REEL7
Description
12- Channel Clock Generator W/Int VCO
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet

Specifications of AD9522-1BCPZ-REEL7

Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.65GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2.5GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 25. Internal VCO Phase Noise (Absolute), LVDS Output @ 662.5 MHz
Figure 24. Internal VCO Phase Noise (Absolute), LVDS Output @ 615 MHz
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
–50
–60
–70
–80
–90
–50
–60
–70
–80
–90
1k
1k
10
Figure 26. Additive (Residual) Phase Noise,
100
CLK-to-LVDS @ 245.76 MHz, Divide-by-1
10k
10k
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
100k
100k
10k
100k
1M
1M
1M
10M
10M
10M
100M
100M
100M
Rev. 0 | Page 23 of 84
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–110
–120
–130
–140
–150
–160
–170
10
10
10
Figure 27. Additive (Residual) Phase Noise,
Figure 28. Additive (Residual) Phase Noise,
Figure 29. Additive (Residual) Phase Noise,
100
100
100
CLK-to-CMOS @ 50 MHz, Divide-by-20
CLK-to-LVDS @ 200 MHz, Divide-by-5
CLK-to-LVDS @ 800 MHz, Divide-by-1
1k
1k
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
10k
10k
10k
100k
100k
100k
1M
1M
1M
AD9522-1
10M
10M
10M
100M
100M
100M

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