AD9522-1BCPZ-REEL7 Analog Devices Inc, AD9522-1BCPZ-REEL7 Datasheet - Page 24

• Manufacturer Part Number: AD9522-1BCPZ-REEL7
• Description: 12- Channel Clock Generator W/Int VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-1BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.65GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.5GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-1
Figure 32. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 2333 MHz;
2458 MHz; PFD = 15.36 MHz; LBW = 40 kHz; LVDS Output = 122.88 MHz
Figure 31. Phase Noise (Absolute) Clock Generation; Internal VCO @
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
–80
–90
PFD = 120 kHz; LBW = 1.92 kHz; LVDS Output = 155.52 MHz
10
1k
1k
INTEGRATED RMS JITTER (12kHz TO 20MHz): 491fs
INTEGRATED RMS JITTER (20kHz TO 80MHz): 368fs (EXTRAPOLATED)
Figure 30. Additive (Residual) Phase Noise,
100
CLK-to-CMOS @ 250 MHz, Divide-by-4
10k
10k
1k
FREQUENCY (Hz)
100k
FREQUENCY (Hz)
100k
FREQUENCY (Hz)
10k
100k
1M
1M
1M
10M
10M
10M
100M
100M
100M
Rev. 0 | Page 24 of 84
Figure 34. PLL Loop Filter Used for Clock Generation Plot (See Figure 31)
@ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVDS Output = 245.76 MHz
Figure 35. PLL Loop Filter Used for Clock Cleanup Plot (See Figure 32)
Figure 33. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
–100
–110
–120
–130
–140
–150
–160
–80
–90
1k
CP
CP
INTEGRATED RMS JITTER (12kHz TO 20MHz): 146fs
10k
CAPACITOR
CAPACITOR
C2
62pF
C2
1.5nF
FOR LDO
FOR LDO
BYPASS
BYPASS
FREQUENCY (Hz)
R1
820Ω
R1
2.1kΩ
100k
C1
240nF
C1
4.7µF
390Ω
3kΩ
R2
R2
C12
220nF
C12
220nF
1M
C3
33pF
C3
2.2nF
LF
BYPASS
LF
BYPASS
10M
100M