AD9522-1BCPZ-REEL7 Analog Devices Inc, AD9522-1BCPZ-REEL7 Datasheet - Page 70

• Manufacturer Part Number: AD9522-1BCPZ-REEL7
• Description: 12- Channel Clock Generator W/Int VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-1BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.65GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.5GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
018
019
019
019
01A
01A
01A
AD9522-1
[0]
[7:6] R, A, B counters
[5:3] R path delay
[2:0] N path delay
[7]
[6]
[5:0] LD pin
VCO calibration
now
SYNC pin reset
Enable STATUS
pin divider
Ref freq monitor
threshold
control
Description
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The
sequence to initiate a calibration follows: program to 0, followed by an IO_UPDATE bit (Register 0x232[0]);
then program to 1, followed by another IO_UPDATE bit (Register 0x232[0]). This sequence gives complete
control over when the VCO calibration occurs relative to the programming of other registers that can impact
the calibration (default = 0). Note that the VCO divider (Register 0x1E0[2:0]) must not be static during VCO
calibration.
[7]
0
0
1
1
R path delay, see Table 2 (default: 0x0).
N path delay, see Table 2 (default: 0x0).
Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the
R and N dividers.
[7] = 0; divide-by-4 disabled on STATUS pin (default).
[7] = 1; divide-by-4 enabled on STATUS pin.
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
frequency monitor’s detection threshold (see Table 17, REF1, REF2, and VCO frequency status monitor parameter).
[6] = 0; frequency valid if frequency is above 1.02 MHz (default).
[6] = 1; frequency valid if frequency is above 8 kHz.
Selects the signal that is connected to the LD pin.
[5] [4] [3]
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
[6]
0
1
0
1
0
0
0
0
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
Action
Do nothing on SYNC (default).
Asynchronous reset.
Synchronous reset.
Do nothing on SYNC.
[2]
0
0
0
0
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
[1]
0
0
1
1
0
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Rev. 0 | Page 70 of 84
[0]
0
1
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Level or
Dynamic
Signal
LVL
DYN
DYN
HIZ
CUR
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
DYN
Ground (dc); for all other cases of 0XXXXX not specified.
Signal at LD Pin
Digital lock detect (high = lock; low = unlock, default).
P-channel, open-drain lock detect (analog lock detect).
N-channel, open-drain lock detect (analog lock detect).
Tristate (high-Z) LD pin.
Current source lock detect (110 μA when DLD is true).
The selections that follow are the same as for REFMON.
Ground (dc).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference);
active high.
Status of unselected reference (not available in differential
mode); active high.
Status of REF1 frequency (active high).
Status of REF2 frequency (active high).
(Status of REF1 frequency) AND (status of REF2 frequency).
(DLD) AND (status of selected reference) AND (status of VCO).
Status of VCO frequency (active high).
Selected reference (low = REF1, high = REF2).
DLD; active high.
Holdover active (active high).
Not available, do not use.
VS (PLL supply).
REF1 clock (differential reference when in differential mode).