AD9874ABSTRL Analog Devices Inc, AD9874ABSTRL Datasheet - Page 10

• Manufacturer Part Number: AD9874ABSTRL
• Description: IC,RF/Baseband Circuit,BICMOS,QFP,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9874ABSTRL

• Rohs Status: RoHS non-compliant
• Function: IF Digitizing Subsystem
• Frequency: 10MHz ~ 300MHz
• Rf Type: UHF, Cellular, TETRA, GSM, EDGE, APCO25
• Secondary Attributes: 16dB Front End Attenuator
• Package / Case: 48-LQFP
• For Use With: AD9874-EB - BOARD EVAL FOR AD9874
• Lead Free Status / Rohs Status: Compliant

AD9874
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f
T
TPC 7a. Normalized Gain Variation
vs. LO Drive (VDDx = 3.0 V)
TPC 8a. Complex FFT of Baseband
I/Q for Single-Tone (High Bias)
TPC 9a. Complex FFT of Baseband
I/Q for Dual Tone IMD (High Bias
with Each IFIN Tone @ –35 dBm)
1
2
3
Data taken with Toko FSLM series 10 µH inductors.
High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01.
Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01.
A
–100
–120
–140
= 25 C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)
–100
–120
–140
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–20
–40
–60
–80
–20
–40
–60
–80
0.1
–80 –60 –40 –20
0
–80 –60 –40 –20
0
0
–20
–18.2dBFS OUTPUT
–2.8dBFS OUTPUT
LOW BIAS
IMD = 74dBc
–17
FREQUENCY – kHz
FREQUENCY – kHz
HIGH BIAS
LO DRIVE – dBm
–14
0
0
–11
MAX VGA ATTEN
NBW = 3.66kHz
MAX VGA ATTEN
20
20
f
DEC–BY–120
NBW = 3.66kHz
CLK
f
DEC–BY–120
CLK
= 18MHz
40
40
= 18MHz
–8
60
60
–5
80
80
TPC 8b. Gain Compression vs. IFIN
(High Bias
TPC 9b. IMD vs. IFIN (High Bias
–100
–106
–112
–118
–124
–130
8.4
7.4
9.0
8.8
8.6
8.2
8.0
7.8
7.6
7.2
7.0
–10
–12
–14
–70
–76
–82
–88
–94
–20
TPC 7b. Noise Figure and IMD
vs. LO Drive (VDDx = 3.0 V)
–2
–4
–6
–8
–51
–30
0
–48
–28
–15
2
)
HARD COMPRESSION
2.7V
–26
–45
LO DRIVE – dBm
ADC GOES INTO
–10
–10–
3.3V
IFIN – dBm
IFIN – dBm
NF-HIGH BIAS
–24
PIN
–42
NF-LOW BIAS
IMD-HIGH BIAS
IMD-LOW BIAS
3.6V
–22
–39
2.7V
–5
3.0V
3.6V
–36
–20
3.3V
0
CLK
–18
3.0V
–33
= 18 MSPS, f
2
)
5
–16
–30
–10
–20
–30
–40
–50
–60
–70
–80
0
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
IF
TPC 7c. Gain Compression vs. IFIN
with 16 dB LNA Attenuator Enabled
TPC 8c. Gain Compression vs. IFIN
(Low Bias
TPC 9c. IMD vs. IFIN (Low Bias
= 109.56 MHz, f
–103
–109
–115
–55
–61
–67
–73
–79
–85
–91
–97
–12
–15
–18
–21
–24
–27
–30
–33
–36
–10
–12
–14
–2
–4
–6
–8
–51
–36
–30
0
–28 –26 –24 –22 –20 –18
–48
ADC DOES NOT GO INTO
–30
HARD COMPRESSION
3
)
2.7V
–45
LO
–24
= 107.4 MHz,
IFIN – dBm
3.3V
1
PIN
–42
IFIN – dBm
IFIN – dBm
HIGH BIAS
–18
3.6V
2.7V
–39
3.6V
3.0V
LOW BIAS
–12
–36
3.3V
3.0V
–33
–6
REV. A
–16
3
)
–30
–14
0
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45