AD9874ABSTRL Analog Devices Inc, AD9874ABSTRL Datasheet - Page 11

IC,RF/Baseband Circuit,BICMOS,QFP,48PIN,PLASTIC

AD9874ABSTRL

Manufacturer Part Number
AD9874ABSTRL
Description
IC,RF/Baseband Circuit,BICMOS,QFP,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9874ABSTRL

Rohs Status
RoHS non-compliant
Function
IF Digitizing Subsystem
Frequency
10MHz ~ 300MHz
Rf Type
UHF, Cellular, TETRA, GSM, EDGE, APCO25
Secondary Attributes
16dB Front End Attenuator
Package / Case
48-LQFP
For Use With
AD9874-EB - BOARD EVAL FOR AD9874
Lead Free Status / Rohs Status
Compliant
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f
T
TPC 10a. Noise Figure vs. BW (Mini-
mum Attenuation, f
TPC 12a. IMD vs. IFIN (f
1
2
3
REV. A
Data taken with Toko FSLM series 10 µH inductors.
High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01.
Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01.
A
–100
–110
–120
–130
–30
–40
–50
–60
–70
–80
–90
= 25 C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)
10.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
–45
9.5
9.0
8.5
8.0
7.5
7.0
TPC 11a. Noise Figure vs. VGA
Attenuation (f
10
0
I/Q DATA
I/Q DATA
24-BIT
–42
16-BIT
CHANNEL BANDWIDTH – kHz
BW = 12.04kHz
–39
(K = 0, M = 8)
VGA ATTENUATION – dB
3
–36
IFIN – dBm
BW = 27.08kHz
(K = 0, M = 3)
PIN
CLK
100
–33
LOW BIAS
CLK
6
= 13 MSPS)
HIGH BIAS
= 13 MSPS)
–30
CLK
ENABLED
I/Q DATA
w/ DVGA
16-BIT
BW = 6.78kHz
(K = 0, M = 15)
= 13 MSPS)
–27
9
–24
1000
12
–5
–10
–15
–20
–25
–30
–35
–40
–45
TPC 10b. Noise Figure vs. BW (Mini-
mum Attenuation, f
TPC 12b. IMD vs. IFIN (f
–100
–110
–120
–130
–30
–40
–50
–60
–70
–80
–90
10.0
9.5
9.0
8.5
8.0
7.5
–45
14
13
12
11
10
10
9
8
7
TPC 11b. Noise Figure vs. VGA
Attenuation (f
0
–42
16-BIT
DATA
CHANNEL BANDWIDTH – kHz
–39
VGA ATTENUATION – dB
(K = 0, M = 2)
3
BW = 50kHz
(K = 0, M = 1)
–36
BW = 75kHz
IFIN – dBm
–11–
PIN
CLK
100
–33
CLK
LOW BIAS
6
= 18 MSPS)
16-BIT DATA
24-BIT
ENABLED
= 18 MSPS)
DATA
–30
CLK
w/ DVGA
HIGH BIAS
(K = 0, M = 9)
BW = 15kHz
= 18 MSPS)
–27
9
CLK
= 18 MSPS, f
–24
1000
12
–5
–10
–15
–20
–25
–30
–35
–40
–45
IF
TPC 10c. Noise Figure vs. BW (Mini-
mum Attenuation, f
TPC 12c. IMD vs. IFIN (f
= 109.56 MHz, f
–100
–110
–120
–130
–30
–40
–50
–60
–70
–80
–90
10.0
9.5
9.0
8.5
8.0
7.5
–45
TPC 11c. Noise Figure vs. VGA
Attenuation (f
14
13
12
11
10
9
8
7
10
0
BW = 90.28kHz
(K = 1, M = 2)
–42
CHANNEL BANDWIDTH – kHz
16-BIT
DATA
–39
VGA ATTENUATION – dB
3
L O
BW = 135.42kHz
–36
= 107.4 MHz,
IFIN – dBm
(K = 1, M = 1)
1
PIN
CLK
100
–33
LOW BIAS
CLK
6
16-BIT DATA
= 26 MSPS)
ENABLED
w/ DVGA
AD9874
= 26 MSPS)
–30
CLK
HIGH BIAS
BW = 27.08kHz
(K = 1, M = 9)
= 26 MSPS)
–27
9
24-BIT
DATA
–24
1000
12
–5
–10
–15
–20
–25
–30
–35
–40
–45

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