ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 21

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

Table 12. Power-Up Sequencing
1
2
3
4
Valid V
Assumes a stable CLKIN signal after meeting worst-case start-up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start-up time.
Based on CLKIN cycles.
CORERST is an internal signal only. The 4096 cycle count is dependent on t
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
depending on the design of the power supply subsystem.
reset time, resulting in 4097 cycles maximum.
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
CORERST
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their V
RESET Low Before V
V
CLKIN Running After valid V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
DSP Core Reset Deasserted After RESET Deasserted
DDINT
on Before V
RESET
V
V
CLKIN
CLK_CFG3-0
CORERST
DDINT
DDEXT
DDEXT
DDINT
/V
t
RSTVDD
DDEXT
DDINT
on
/V
Rev. B | Page 21 of 60 | February 2010
DDEXT
Figure 8. Power-Up Sequencing
t
IVDDEVDD
t
CLKVDD
1
DDINT
SRST
and V
specification. If setup time is not met, one additional CLKIN cycle may be added to the core
DDEXT
t
PLLRST
t
CLKRST
rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds,
t
CORERST
ADSP-21160M/ADSP-21160N
Min
0
– 50
0
10
20
4096t
2
3
CK
3, 4
Max
+200
200
Unit
ns
ms
ms
μs
μs
ms