ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 43

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

Serial Ports
For serial ports, see
Table
mine whether communication is possible between two devices
Table 29. Serial Ports—External Clock
1
2
3
Table 30. Serial Ports—Internal Clock
1
2
Table 31. Serial Ports—External or Internal Clock
1
Table 32. Serial Ports—External Clock
1
Parameter
Timing Requirements
t
t
t
t
t
t
Referenced to sample edge.
For ADSP-21160M, specification is 4 ns, minimum.
For ADSP-21160M, specification is 14 ns, minimum.
Parameter
Timing Requirements
t
t
t
t
Referenced to sample edge.
For ADSP-21160M, specification is 1 ns, minimum
Parameter
Switching Characteristics
t
t
Referenced to drive edge.
Parameter
Switching Characteristics
t
t
t
t
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
SFSI
HFSI
SDRI
HDRI
DFSE
HOFSE
DFSE
HOFSE
DDTE
HDTE
33,
Table
34,
Table
TFS/RFS Setup Before TCLK/RCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
TCLK/RCLK Width
TCLK/RCLK Period
TFS Setup Before TCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
RFS Delay After RCLK (Internally Generated RFS)
RFS Hold After RCLK (Internally Generated RFS)
TFS Delay After TCLK (Internally Generated TFS)
TFS Hold After TCLK (Internally Generated TFS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
Table
35,
29,
Figure
Table
30,
26, and
3
Table
1
; RFS Setup Before RCLK
Figure
31,
1, 2
1
Table
1
1
1, 2
1
Rev. B | Page 43 of 60 | February 2010
27. To deter-
1
1
1
32,
1
1
1
1
1
at clock speed n, the following specifications must be confirmed:
1) frame sync delay and frame sync setup and hold, 2) data delay
and data setup and hold, and 3) SCLK width.
Min
3.5
4
1.5
6.5
8
2t
Min
8
t
6.5
3
Min
3
Min
3
0
CCLK
CCLK
ADSP-21160M/ADSP-21160N
/2 + 1
Max
Max
13
Max
13
16
Max
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
Unit
ns
ns
ns
ns