ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 41

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

Link Ports—Receive, Transmit
For link ports, see
Calculation of link receiver data setup and hold, relative to link
clock, is required to determine the maximum allowable skew
that can be introduced in the transmission path, between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA, relative to LCLK (setup
skew = t
Table 27. Link Ports—Receive
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
For ADSP-21160M, specification is 2.5 ns, minimum.
For ADSP-21160M, specification is 6 ns, minimum.
For ADSP-21160M, specification is 6 ns, minimum.
LACK goes low with t
For ADSP-21160M, specification is 12 ns, minimum.
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLALC
LCLKTWH
LCLK
LDAT(7:0)
LACK (OUT)
minimum – t
DLALC
Table
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period
LCLK Width Low
LCLK Width High
LACK Low Delay After LCLK High
relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.
27,
Table
DLDCH
RECEIVE
28,
– t
2
3
Figure
SLDCL
). Hold skew is the
24, and
1
t
LCLKRWH
Rev. B | Page 41 of 60 | February 2010
4, 5
Figure
Figure 24. Link Ports—Receive
t
SLDCL
IN
25.
t
LCLKIW
t
HLDCL
maximum delay that can be introduced in LCLK, relative to
LDATA (hold skew = t
culations made directly from speed specifications result in
unrealistically small skew times, because they include multiple
tester guardbands.
Note that there is a two-cycle effect latency between the link
port enable instruction and the DSP enabling the link port.
t
LCLKRWL
Min
2.5
3
t
4
4
9
LCLK
ADSP-21160M/ADSP-21160N
t
DLALC
LCLKTWL
minimum + t
Max
17
HLDCH
– t
Unit
ns
ns
ns
ns
ns
ns
HLDCL
). Cal-