ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 4

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160M/ADSP-21160N
GENERAL DESCRIPTION
The ADSP-21160x SHARC
ADSP-21160M and ADSP-21160N. The ADSP-21160M is fabri-
cated in a 0.25 micron CMOS process. The ADSP-21160N is
fabricated in a 0.18 micron CMOS process. The ADSP-21160N
offers higher performance and lower power consumption than
the ADSP-21160M. Easing portability, the ADSP-21160x is
application source code compatible with first generation
ADSP-2106x SHARC DSPs in SISD (single instruction, single
data) mode. To take advantage of the processor’s SIMD (single-
instruction, multiple-data) capability, some code changes are
needed. Like other SHARC DSPs, the ADSP-21160x is a 32-bit
processor that is optimized for high performance DSP applica-
tions. The ADSP-21160x includes a core running up to
100 MHz, a dual-ported on-chip SRAM, an integrated I/O pro-
cessor with multiprocessing support, and multiple internal
buses to eliminate I/O bottlenecks.
Table 1
and ADSP-21160N processors.
Table 1. ADSP-21160x SHARC Processor Family Features
The ADSP-21160x introduces single-instruction, multiple-data
(SIMD) processing. Using two computational units
(ADSP-2106x SHARC DSPs have one), the ADSP-21160x can
double performance versus the ADSP-2106x on a range of DSP
algorithms.
Fabricated in a state-of-the-art, high speed, low power CMOS
process, the ADSP-21160N has a 10 ns instruction cycle time.
With its SIMD computational hardware running at 100 MHz,
the ADSP-21160N can perform 600 million math operations
per second (480 million operations for ADSP-21160M at a
12.5 ns instruction cycle time).
Table 2
These benchmarks provide single-channel extrapolations of
measured dual-channel (SIMD) processing performance. For
more information on benchmarking and optimizing DSP code
for single- and dual-channel processing, see the Analog Devices
website (www.analog.com).
The ADSP-21160x continues the SHARC family’s industry-
leading standards of integration for DSPs, combining a high
performance 32-bit DSP core with integrated, on-chip system
features. These features include a 4M-bit dual-ported SRAM
memory, host processor interface, I/O processor that supports
14 DMA channels, two serial ports, six link ports, external par-
allel bus, and glueless multiprocessing.
Feature
SRAM
Operating Voltage
Instruction Rate
Link Port Transfer Rate (6)
Serial Port Transfer Rate (2)
shows major differences between the ADSP-21160M
shows performance benchmarks for the ADSP-21160x.
®
DSP family has two members:
ADSP-21160M
4 Mbits
3.3 V I/O
2.5 V Core
80 MHz
80 MBytes/s
40 Mbits/s
4 Mbits
3.3 V I/O
1.9 V Core
100 MHz
100 MBytes/s
50 Mbits/s
ADSP-21160N
Rev. B | Page 4 of 60 | February 2010
Table 2. ADSP-21160x Benchmarks
The functional block diagram
ADSP-21160x illustrates the following architectural features:
Figure 2
cessing system appears in
ADSP-21160X FAMILY CORE ARCHITECTURE
The ADSP-21160x processor includes the following architec-
tural features of the ADSP-2116x family core. The
ADSP-21160x is code compatible at the assembly level with the
ADSP-2106x and ADSP-21161.
SIMD Computational Engine
The ADSP-21160x contains two computational processing ele-
ments that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and
PEY, and each contains an ALU, multiplier, shifter, and register
file. PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
Benchmark Algorithm
1024 Point Complex FFT
(Radix 4, with reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
• Two processing elements, each made up of an ALU, multi-
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
• Interval timer
• On-chip SRAM (4M bits)
• External port that supports:
• DMA controller
• Serial ports and link ports
• JTAG test access port
plier, shifter, and data register file
transfers between memory and the core every core proces-
sor cycle
• Interfacing to off-chip memory peripherals
• Glueless multiprocessing support for six
• Host port
shows a typical single-processor system. A multipro-
ADSP-21160x SHARC DSPs
Figure 5 on Page
115 μs
6.25 ns
25 ns
56.25 ns
100 ns
37.5 ns
56.25 ns
560M bytes/s
(Figure 1 on Page
ADSP-21160M
80 MHz
9.
92 μs
5 ns
20 ns
45 ns
80 ns
30 ns
45 ns
800M bytes/s
1) of the
ADSP-21160N
100 MHz