ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 28

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160M/ADSP-21160N
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without reference
to CLKIN except for the ACK pin requirements listed in note 1
Table 19. Memory Write—Bus Master
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register) × t
H = t
HI = t
I = t
For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory
The falling edge of MSx, BMS is referenced.
For ADSP-21160M, specification is t
See
DAAK
DSAK
SAKC
HAKC
DAWH
DAWL
WW
DDWH
DWHA
DWHD
DATRWH
WWR
DDWR
WDE
access, ACK must be driven low (deasserted) by t
t
HAKC
Example System Hold Time Calculation on Page 49
CK
CK
CK
must be met for both assertion and deassertion of ACK signal
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
ACK Delay from Address, Selects
ACK Delay from WRx Low
ACK Setup to CLKIN
ACK Hold After CLKIN
Address, CIF, Selects to WRx Deasserted
Address, CIF, Selects to WRx Low
WRx Pulsewidth
Data Setup before WRx High
Address Hold after WRx Deasserted
Data Hold after WRx Deasserted
Data Disable after WRx Deasserted
WRx High to WRx, RDx, DMAGx Low
Data Disable before WRx or RDx Low
WRx Low to Data Enabled
CK
–0.25t
CCLK
1
–12.5+W ns, minimum.
DAAK
1
or t
1
for calculation of hold times given capacitive and dc loads.
DSAK
3
or t
Rev. B | Page 28 of 60 | February 2010
1, 2
2
SAKC
4
. For the second and subsequent cycles of an asynchronous external memory access, the t
CK
.
2
Min
0.5t
1
t
0.25t
t
t
0.25t
0.25t
0.25t
0.5t
0.25t
–0.25t
CK
CK
CK
– 0.25t
– 0.5t
– 0.5t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
+3
– 1+HI
of
is the bus master accessing external memory space in asynchro-
nous access mode.
CCLK
CCLK
– 3
– 1+H
– 1+H
– 2+H
– 1+I
CCLK
– 1
Table
– 1+W
– 1+W
– 3+W
19. These specifications apply when the ADSP-21160x
Max
t
t
0.25t
CK
CK
– 0.75t
– 0.5t
CCLK
CCLK
+2+H
CCLK
–12+W
– 11+W
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SAKC
and