ADSP-BF504BCPZ-4 Analog Devices Inc, ADSP-BF504BCPZ-4 Datasheet - Page 10

• Manufacturer Part Number: ADSP-BF504BCPZ-4
• Description: Low Cost Blackfin Wtih Processor Only
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-4

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 68kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
UP/DOWN COUNTERS AND
THUMBWHEEL INTERFACES
Two 32-bit up/down counters are provided that can sense 2-bit
quadrature or binary codes as typically emitted by industrial
drives or manual thumbwheels. The counters can also operate
in general-purpose up/down count modes. Then, count direc-
tion is either controlled by a level-sensitive input pin or by two
edge detectors.
A third counter input can provide flexible zero marker support
and can alternatively be used to input the push-button signal of
thumb wheels. All three pins have a programmable debouncing
circuit.
Internal signals forwarded to each timer unit enable these tim-
ers to measure the intervals between count events. Boundary
registers enable auto-zero operation or simple system warning
by interrupts when programmable count values are exceeded.
3-PHASE PWM UNITS
The two/dual 3-phase PWM generation units each feature:
Each PWM block integrates a flexible and programmable
3-phase PWM waveform generator that can be programmed
to generate the required switching patterns to drive a 3-phase
voltage source inverter for ac induction motor (ACIM) or
permanent magnet synchronous motor (PMSM) control. In
addition, the PWM block contains special functions that
considerably simplify the generation of the required PWM
switching patterns for control of the electronically commutated
motor (ECM) or brushless dc motor (BDCM). Software can
enable a special mode for switched reluctance motors (SRM).
• 16-bit center-based PWM generation unit
• Programmable PWM pulse width
• Single/double update modes
• Programmable dead time and switching frequency
• Twos-complement implementation which permits smooth
• Possibility to synchronize the PWM generation to either
• Special provisions for BDCM operation (crossover and
• Wide variety of special switched reluctance (SR) operating
• Output polarity and clock gating control
• Dedicated asynchronous PWM shutdown signal
transition to full ON and full OFF states
externally-generated or internally-generated synchroniza-
tion pulses
output enable functions)
modes
Rev. 0 | Page 10 of 80 | December 2010
The six PWM output signals (per PWM unit) consist of three
high-side drive signals (PWMx_AH, PWMx_BH, and
PWMx_CH) and three low-side drive signals (PWMx_AL,
PWMx_BL, and PWMx_CL). The polarity of the generated
PWM signal can be set with software, so that either active HI or
active LO PWM patterns can be produced.
The switching frequency of the generated PWM pattern is pro-
grammable using the 16-bit PWM_TM register. The PWM
generator can operate in single update mode or double update
mode. In single update mode, the duty cycle values are pro-
grammable only once per PWM period, so that the resultant
PWM patterns are symmetrical about the midpoint of the PWM
period. In the double update mode, a second updating of the
PWM registers is implemented at the midpoint of the PWM
period. In this mode, it is possible to produce asymmetrical
PWM patterns that produce lower harmonic distortion in
3-phase PWM inverters.
Pulses synchronous to the switching frequency can be generated
internally and output on the PWMx_SYNC pin. The PWM unit
can also accept externally generated synchronization pulses
through PWMx_SYNC.
Each PWM unit features a dedicated asynchronous shutdown
pin, PWMx_TRIP, which (when brought low) instantaneously
places all six PWM outputs in the OFF state.
SERIAL PORTS
The processors incorporate two dual-channel synchronous
serial ports (SPORT0 and SPORT1) for serial and multiproces-
sor communications. The SPORTs support the following
features:
• I
• Bidirectional operation—Each SPORT has two sets of inde-
• Buffered (8-deep) transmit and receive ports—Each port
• Clocking—Each transmit and receive port can either use an
• Word length—Each SPORT supports serial data words
• Framing—Each transmit and receive port can run with or
• Companding in hardware—Each SPORT can perform
pendent transmit and receive pins, enabling eight channels
of I
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
external serial clock or generate its own, in frequencies
ranging from (f
from 3 to 32 bits in length, transferred most significant bit
first or least significant bit first.
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without
additional latencies.
2
S capable operation.
2
S stereo audio.
SCLK
/131,070) Hz to (f
SCLK
/2) Hz.