ADSP-BF504BCPZ-4 Analog Devices Inc, ADSP-BF504BCPZ-4 Datasheet - Page 19

• Manufacturer Part Number: ADSP-BF504BCPZ-4
• Description: Low Cost Blackfin Wtih Processor Only
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-4

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 68kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

is necessary to read from both D
Figure 7 (ADC (Internal), ACM, and SPORT
shows both D
the processor’s serial ports. The SPORTx Receive Configuration
1 register and SPORTx Receive Configuration 2 register should
be set up as outlined in
ration 1 Register
Receive Configuration 2 Register
Table 9. The SPORTx Receive Configuration 1 Register
(SPORTx_RCR1)
NOTE: The SPORT must be enabled with the following set-
tings: external clock, external frame sync, and active low frame
sync.
Table 10. The SPORTx Receive Configuration 2 Register
(SPORTx_RCR2)
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst. A Blackfin driver for the
ADC is available to download at www.analog.com.
INTERNAL ADC
An ADC is integrated into the ADSP-BF506F product. All ADC
signals are connected out to package pins to enable maximum
interconnect flexibility in mixed signal applications.
The internal ADC is a dual, 12-bit, high speed, low power, suc-
cessive approximation ADC that operates from a single 2.7 V to
5.25 V power supply and features throughput rates up to
2 MSPS. The device contains two ADCs, each preceded by a
3-channel multiplexer, and a low noise, wide bandwidth track-
and-hold amplifier that can handle input frequencies in excess
of 30 MHz.
Figure 8
ADC. The ADC features include:
Setting
RCKFE = 1
LRFS = 1
RFSR = 1
IRFS = 0
RLSBIT = 0
RDTYPE = 00
IRCLK = 0
RSPEN = 1
TFSR = RFSR = 1
Setting
RXSE = 1
SLEN = 1111
• Dual 12-bit, 3-channel ADC
• Throughput rate: up to 2 MSPS
• Specified for DV
shows the functional block diagram of the internal
OUT
(SPORTx_RCR1)) and
A and D
DD
Description
Sample data with rising edge of RSCLK
Active low frame signal
Frame every word
External RFS used
Receive MSB first
Zero fill
External receive clock
Receive enabled
Description
Secondary side enabled
16-bit data-word (or may be set to 1101 for
14-bit data-word)
Table 9 (The SPORTx Receive Configu-
and AV
OUT
B of the ADC connected to one of
DD
OUT
(SPORTx_RCR2)).
of 2.7 V to 5.25 V
pins simultaneously.
Table 10 (The SPORTx
Connections)
Rev. 0 | Page 19 of 80 | December 2010
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
The conversion process and data acquisition use standard con-
trol inputs allowing easy interfacing to microprocessors or
DSPs. The input signal is sampled on the falling edge of CS; con-
version is also initiated at this point. The conversion time is
determined by the ADSCLK frequency. There are no pipelined
delays associated with the part.
The internal ADC uses advanced design techniques to achieve
very low power dissipation at high throughput rates. The part
also offers flexible power/throughput rate management when
operating in normal mode as the quiescent current consump-
tion is so low.
The analog input range for the part can be selected to be a 0 V to
V
complement output coding. The internal ADC has an on-chip
2.5 V reference that can be overdriven when an external refer-
ence is preferred.
REF
• Pin-configurable analog inputs
• Accurate on-chip voltage reference: 2.5 V
• Dual conversion with read 437.5 ns, 32 MHz ADSCLK
• High speed serial interface
• Low power shutdown mode
V
V
V
V
V
V
V
V
V
V
V
V
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
(or 2 × V
AGND AGND AGND D
• 12-channel single-ended inputs
• 6-channel fully differential inputs
• 6-channel pseudo differential inputs
• SPI-/QSPI
REF SELECT
or
or
MUX
MUX
REF
Figure 8. ADC (Internal) Functional Block Diagram
REF
) range, with either straight binary or twos
BUF
BUF
T/H
T/H
TM
-/MICROWIRE
CAP
APPROXIMATION
APPROXIMATION
B
SUCCESSIVE
SUCCESSIVE
D
CONTROL
CAP
LOGIC
12-BIT
12-BIT
ADC
ADC
A
DGND
AV
TM
-/DSP-compatible
DD
ADC
DRIVERS
DRIVERS
OUTPUT
OUTPUT
DGND
DV
DD
D
ADSCLK
CS
RANGE
SGL/DIFF
A0
A1
A2
V
D
DRIVE
OUT
OUT
A
B