ADSP-BF504BCPZ-4 Analog Devices Inc, ADSP-BF504BCPZ-4 Datasheet - Page 32

• Manufacturer Part Number: ADSP-BF504BCPZ-4
• Description: Low Cost Blackfin Wtih Processor Only
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-4

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 68kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
PROCESSOR—TIMING SPECIFICATIONS
Specifications subject to change without notice.
Clock and Reset Timing
Table 24
the CCLK and SCLK timing specifications in
Table
not select core/peripheral clocks in excess of the processor’s
speed grade.
Table 24. Clock and Reset Timing
1
2
3
4
5
6
Parameter
Timing Requirements
f
t
t
t
Switching Characteristic
t
Applies to PLL bypass mode and PLL non bypass mode.
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
The t
If the DF bit in the PLL_CTL register is set, the minimum f
Applies after power-up sequence is complete. See
The ADSP-BF504/ADSP-BF504F/ADSP-BF506F processor does not have a dedicated CLKBUF pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or
CKIN
CKINL
CKINH
WRST
BUFDLAY
Table 16 on Page
CLKOUT. This parameter applies when EXTCLK is programmed to output CLKBUF.
CKIN
16, combinations of CLKIN and clock multipliers must
period (see
and
Table 25
Figure 10
26.
CLKBUF
Figure
CLKIN
CLKIN Frequency
CLKIN Frequency
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
CLKIN to CLKBUF
and
10) equals 1/f
describe clock and reset operations. Per
Figure 11
t
CKINL
CKIN
1
describe clock out timing.
1, 2, 3, 4
1, 2, 3, 4
6
1
.
t
Delay
CKIN
Table 26
t
(Commercial/Industrial Models) 12
(Automotive Models)
CKINH
Table 14
CKIN
and
Rev. 0 | Page 32 of 80 | December 2010
specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
Figure 12
5
Figure 10. Clock and Reset Timing
to
t
WRST
for power-up reset timing.
Min
14
10
10
11 × t
VCO
CKIN
, f
CCLK
t
BUFDLAY
, and f
SCLK
settings discussed in
Max
50
50
11
Table 14 on Page 26
t
BUFDLAY
through
ns
ns
Unit
MHz
MHz
ns
ns