ADSP-BF504BCPZ-4 Analog Devices Inc, ADSP-BF504BCPZ-4 Datasheet - Page 48

• Manufacturer Part Number: ADSP-BF504BCPZ-4
• Description: Low Cost Blackfin Wtih Processor Only
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-4

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 68kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
JTAG Test And Emulation Port Timing
Table 42
Table 42. JTAG Port Timing
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
Applies to System Inputs = PF15–0, PG15–0, PH2–0, NMI, BMODE3–0, RESET.
Applies to TWI System Inputs = SCL, SDA. For SDA and SCL system inputs, the system design must comply with V
50 MHz Maximum
System Outputs = EXTCLK, SCL, SDA, PF15–0, PG15–0, PH2–0.
TCK
STAP
HTAP
SSYS
STWI
HSYS
TRSTW
DTDO
DSYS
TWI_DT (000) setting in
and
OUTPUTS
SYSTEM
SYSTEM
INPUTS
TMS
TDO
TCK
Figure 31
TDI
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
TWI System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
Table
describe JTAG port operations.
13.
3
(measured in TCK cycles)
t
DSYS
t
DTDO
t
TCK
1
Rev. 0 | Page 48 of 80 | December 2010
4
t
1
SSYS
t
STAP
2
Figure 31. JTAG Port Timing
t
HTAP
t
HSYS
Min
20
4
4
4
n/a
5
4
V
DDEXT
= 1.8 V
Max
10
12
DDEXT
and VBUSTWI voltages specified for the default
Min
20
4
4
4
5
5
4
V
DDEXT
= 2.5 V/3.3 V
Max
10
12
Unit
ns
TCK
ns
ns
ns
ns
ns
ns
ns