ADSP-BF504BCPZ-4 Analog Devices Inc, ADSP-BF504BCPZ-4 Datasheet - Page 3

• Manufacturer Part Number: ADSP-BF504BCPZ-4
• Description: Low Cost Blackfin Wtih Processor Only
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-4

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 68kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GENERAL DESCRIPTION
The ADSP-BF50x processors are members of the Blackfin
ily of products, incorporating the Analog Devices/Intel Micro
Signal Architecture (MSA). Blackfin processors combine a dual-
MAC state-of-the-art signal processing engine, the advantages
of a clean, orthogonal RISC-like microprocessor instruction set,
and single-instruction, multiple-data (SIMD) multimedia capa-
bilities into a single instruction-set architecture.
The ADSP-BF50x processors are completely code compatible
with other Blackfin processors. ADSP-BF50x processors offer
performance up to 400 MHz and reduced static power con-
sumption. Differences with respect to peripheral combinations
are shown in
Table 1. Processor Comparison
1
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
Feature
Up/Down/Rotary Counters
Timer/Counters with PWM
3-Phase PWM Units
SPORTs
SPIs
UARTs
Parallel Peripheral Interface
Removable Storage Interface
CAN
TWI
Internal 32M Bit Flash
ADC Control Module (ACM)
Internal ADC
GPIOs
Maximum Speed Grade
Maximum System Clock Speed
Package Options
For valid clock combinations, see
L1 Instruction SRAM
L1 Instruction SRAM/Cache
L1 Data SRAM
L1 Data SRAM/Cache
L1 Scratchpad
L3 Boot ROM
Table
1.
1
Table
14,
88-Lead
LFCSP
16K
16K
16K
16K
Table
35
4K
4K
2
2
2
2
2
1
1
1
8
1
1
–
–
15,
Table
400 MHz
100 MHz
88-Lead
LFCSP
16K
16K
16K
16K
4K
35
4K
2
8
2
2
2
2
1
1
1
1
1
1
–
16, and
Rev. 0 | Page 3 of 80 | December 2010
120-Lead
Table 24
LQFP
16K
16K
16K
16K
®
35
4K
4K
2
8
2
2
2
2
1
1
1
1
1
1
1
fam-
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which provides the ability to vary both the
voltage and frequency of operation to significantly lower overall
power consumption. This capability can result in a substantial
reduction in power consumption, compared with just varying
the frequency of operation. This allows longer battery life for
portable appliances.
SYSTEM INTEGRATION
The ADSP-BF50x processors are highly integrated system-on-a-
chip solutions for the next generation of embedded industrial,
instrumentation, and power/motion control applications. By
combining industry-standard interfaces with a high perfor-
mance signal processing core, cost-effective applications can be
developed quickly, without the need for costly external compo-
nents. The system peripherals include a watchdog timer; two
32-bit up/down counters with rotary support; eight 32-bit tim-
ers/counters with PWM support; six pairs of 3-phase 16-bit
center-based PWM units; two dual-channel, full-duplex syn-
chronous serial ports (SPORTs); two serial peripheral interface
(SPI) compatible ports; two UARTs with IrDA
allel peripheral interface (PPI); a removable storage interface
(RSI) controller; an internal ADC with 12 channels, 12 bits, up
to 2 MSPS, and ACM controller; a controller area network
(CAN) controller; a 2-wire interface (TWI) controller; and an
internal 32M bit flash.
PROCESSOR PERIPHERALS
The ADSP-BF50x processors contain a rich set of peripherals
connected to the core via several high-bandwidth buses, provid-
ing flexibility in system configuration as well as excellent overall
system performance (see the block diagram
Blackfin processors contain high-speed serial and parallel ports,
an interrupt controller for flexible management of interrupts
from the on-chip peripherals or external sources, and power
management control functions to tailor the performance and
power characteristics of the processor and system to many
application scenarios.
The SPORT, SPI, UART, PPI, and RSI peripherals are sup-
ported by a flexible DMA structure. There are also separate
memory DMA channels dedicated to data transfers between the
processor’s various memory spaces, including boot ROM and
internal 32M bit synchronous burst flash. Multiple on-chip
buses running at up to 100 MHz provide enough bandwidth to
keep the processor core running along with activity on all of the
on-chip and external peripherals.
The ADSP-BF50x processors include an interface to an off-chip
voltage regulator in support of the processor’s dynamic power
management capability.
on Page
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support; a par-
1). These